AI Chips: NoC Interconnect IP Solves Three Design Challenges

By Kurt Shuler - 10 Jan, 2019 - Comments: 0

New network-on-chip (NoC) interconnect IP is now available for artificial intelligence (AI) systems-on-chip (SoC). Arteris IP launched the fourth generation of the FlexNoC interconnect IP with a new optional AI package. The novel NoC interconnect technologies solves many data flow problems in today’s AI designs. Innovative features address the requirements of the next-generation of AI chips t... » read more

Adding NoCs To FPGA SoCs

By Ann Mutschler - 28 Jun, 2018 - Comments: 0

FPGA SoCs straddle the line between flexibility and performance by combining elements of both FPGAs and ASICs. But as they find a home in more safety- and mission-critical markets, they also are facing some of the same issues as standard SoCs, including the ability to move larger and larger amounts of data quickly throughout an increasingly complex device, and the difficulty in verifying and de... » read more

Avoiding Traffic Jams In SoC Design

By Kurt Shuler - 28 Aug, 2017 - Comments: 0

While sitting in a traffic jam on the way to work, I realized that the sheer volume of vehicles on the road exceeds the capacity originally planned for by civil engineers, when highways first hit the drawing boards 50 or 60 years ago. It dawned on me that there is a parallel to today’s System-on-Chip design—engineers are struggling to close timing on the interconnect during the back-end pla... » read more

OSDN – On-chip Software Defined Network

By Rajesh Ramanujam - 27 Oct, 2016 - Comments: 0

You must be mumbling to yourself, “Oh no, not another NoC article! The term NoC is used so loosely in the industry and everybody seem to be claiming they have one, so what more is there to say?” Fair enough, but please indulge me. Actually, there are some wannabe NoCs out there, but very few actually provide a full-fledged network. I submit, a real NoC should implement all the same key d... » read more

Executive Insight: Sundari Mitra

By Ed Sperling - 20 Sep, 2016 - Comments: 0

Sundari Mitra, co-founder and CEO of [getentity id="22535" e_name="NetSpeed Systems"], sat down with Semiconductor Engineering to discuss machine learning, shifting from a processor-centric to a memory-centric design, and what needs to change to make that all happen. What follows are excerpts of that conversation. SE: What is the biggest change you’re seeing? Mitra: We go through a cycl... » read more

Adapt Or Perish: A Unified Theory Of Coherency

By Rajesh Ramanujam - 28 Jul, 2016 - Comments: 0

Evolution is a natural process and more importantly a relatively slow process that has eventually got us here, capable of perceiving, analyzing, and handling complex tasks. As our environment, society, and surroundings became more complex we learned how to adapt at a brisk and instantaneous manner, in this melting pot of a heterogeneous world. The evidence can be seen in all ages, from the poli... » read more

Top Mobile OEM Uses NetSpeed to Boost Its Next Gen Application Processor

By NetSpeed Systems - 29 Jun, 2016 - Comments: 0

The smartphone segment is certainly the most competitive market for chip makers today and the yearly product launch cadence puts a lot of pressure on the application processor design cycle. End-users expect to benefit from higher image definition, better sound quality, ever faster and more complex applications which push the limits of application processor performance in terms of higher frequen... » read more

Automating Front-End SoC Design With NetSpeed’s On-Chip-Network IP

By NetSpeed Systems - 27 Apr, 2016 - Comments: 0

This white paper from The Linley Group examines the challenges of turning SoC architecture specifications into successful design implementations. It presents the case that SoCs are becoming too large and complex for existing design methodologies and identifies the need for a more automated front-end design process. To read more, click here. » read more

Optimizing Enterprise-Class SSD Host Controller Design With Arteris FlexNoC Network-On-Chip Interconnect IP

By Arteris - 26 Feb, 2016 - Comments: 0

Solid state storage is rapidly supplanting rotary storage in data center computing, driven by the competing needs for lower power consumption, lower latency and higher bandwidth. But the inherent unreliability of flash cells mandates the use of sophisticated host controllers to guarantee data reliability and endurance for enterprise solid state disks (SSD). Leading enterprise SSD companies have... » read more

Top 5 Reasons The SoC Interconnect Matters

By Kurt Shuler - 29 Oct, 2015 - Comments: 0

The on-chip interconnect is the one area of SoC design that still does not receive the priority that it deserves. It’s like Rodney Dangerfield: It gets no respect. However, that is changing because of rising chip complexity, smaller process dimensions, and acknowledgement of the fact that in a world where design teams commercially license most of the chip’s critical semiconductor IP (like C... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: network on chip