tag: NoC

NoC Obfuscation For Protecting Against Reverse Engineering Attacks (U. Of Florida)
By Technical Paper Link - 20 Jul, 2023 - Comments: 0

A technical paper titled "ObNoCs: Protecting Network-on-Chip Fabrics Against Reverse-Engineering Attacks" was published by researchers at University of Florida. Abstract: "Modern System-on-Chip designs typically use Network-on-Chip (NoC) fabrics to implement coordination among integrated hardware blocks. An important class of security vulnerabilities involves a rogue foundry reverse-engineeri... » read more

The Architect’s Dilemma And Closing The Loop With Implementation
By Frank Schirrmeister - 06 Apr, 2023 - Comments: 0

Gordon Moore has left a mark on our industry. Moore's Law has shaped decades of development. The EDA industry has been moving up the layers of abstraction to increase the productivity and predictability of design flows in our efforts to address the ever-increasing complexity of semiconductors and electronics developments. I had written about it in "Chasing The Next Level Of Productivity" not lo... » read more

Physically Aware NoCs
By Ed Sperling - 06 Mar, 2023 - Comments: 0

More functions, greater security risks, and increasingly complicated integration of IP and various components below 7nm is increasing the time and effort it takes to get a functioning chip out the door. In many of these devices, the network on chip is the glue between various components, but it can take up to 10% to 12% of the total area of the SoC. Andy Nightingale, vice president of product m... » read more

The Game Of Ecosystems Intensifies
By Frank Schirrmeister - 02 Mar, 2023 - Comments: 0

You may know about my fascination with ecosystems if you have followed my writing. It is only fitting that I am writing this Blog in Munich (shiver, it's cold), where I attended the GSA McKinsey workshop on "Distributed E/E Architectures and Zonal Computing." This workshop had attendees from semiconductor foundries, EDA vendors, IP vendors, Tier 1 Semis, Tier 2 Integrators, software vendors, an... » read more

Considering Semiconductor Implementation Aspects Early During Network-on-Chip Development
By Frank Schirrmeister - 22 Feb, 2023 - Comments: 1

As they say, while history may not repeat itself, it sure rhymes. In 2015, I wrote the blog "Why Implementation Matters To System Design And Software." At the time, I mused that while abstraction is essential in system design, it has limitations that users must consider. Critical decisions, such as those regarding power and performance, require more accuracy than can be feasibly abstracted. ... » read more

Shortening Network-on-Chip Development Schedules Using Physical Awareness
By Frank Schirrmeister - 05 Jan, 2023 - Comments: 0

Taking physical design into account as early as possible has been a consideration of chip development teams for quite some time. Still, in interactions with customers and partners, 2022 marked a sharp uptick in concerns about whether a design that may be functionally correct can also be implemented using physical implementation flows. Given the intricacies and complexity of network-on-chip (NoC... » read more

When Does My SoC Design Need A NoC?
By Michael Frank - 01 Dec, 2022 - Comments: 0

By Michael Frank and Frank Schirrmeister Excluding the simplest offerings, almost every modern system-on-chip (SoC) device will implement its on-chip communications utilizing a network-on-chip (NoC). Some people question whether it is necessary to use a NoC or whether a more basic approach would suffice. What is in an SoC? An SoC is an integrated circuit (IC) that incorporates most or all ... » read more

Fast and Flexible FPGA-based NoC Hybrid Emulation
By Technical Paper Link - 14 Jul, 2022 - Comments: 0

Researchers from RWTH Aachen University and Otto-von-Guericke Universitat Magdeburg have published a new technical paper titled "EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs." Abstract: "Networks-on-Chips (NoCs) recently became widely used, from multi-core CPUs to edge-AI accelerators. Emulation on FPGAs promises to accelerate their RTL modeling co... » read more

TU Dresden: Tile-based Multi-Core Architecture for Heterogeneous RISC-V Processors Suitable for FPGA Platforms
By Technical Paper Link - 04 Jul, 2022 - Comments: 0

New technical paper titled "AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors" from researchers at Technische Universitaet Dresden (TU Dresden). Partial Abstract: "In this work, AGILER is proposed as an adaptive tile-base many-core architecture for heterogeneous RISC-V based processors. The proposed architecture consists of modular and adaptable heter... » read more

A New Breed Of EDA Required
By Brian Bailey - 23 Jun, 2022 - Comments: 1

While doing research for one of my stories this month, a couple of people basically said that applying methodologies of the past to the designs of today can be problematic because there are fundamental differences in the architectures and workloads. While I completely agree, I don't think these statements go far enough. Designs of today generally have one of everything — one CPU, one accel... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy