Chip Industry Technical Paper Roundup: Mar. 9


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations FHECore: Rethinking GPU Microarchitecture for Fully Homomorphic Encryption 🔗 Boston University, Northeastern University, KAIST, University of Murcia Heterogeneous Memory Design Exploration for AI Accelerators with a Gain Cell Memory Compiler ... » read more

A GPU Microarchitecture Optimized for Fully Homomorphic Encryption


Researchers from Boston University, Northeastern University, KAIST, and University of Murcia, et al. have released “FHECore: Rethinking GPU Microarchitecture for Fully Homomorphic Encryption”. Abstract“Fully Homomorphic Encryption (FHE) enables computation directly on encrypted data but incurs massive computational and memory overheads, often exceeding plaintext execution by seve... » read more

Chip Industry Week in Review


The IEEE ISSCC conference was held this week in San Francisco. Among the highlights: IBM detailed an AI accelerator based on its new inferencing dataflow architecture. CEA-Leti presented a chip-scale, ultra-fast, battery-operated EPR spectrometer. QuTech introduced a cryo-CMOS SoC with NV centers in diamond. UTokyo showed its low-jitter PLL architecture for beyond 5G/6G. Imec d... » read more

Research Bits: Feb. 3


Artificial synapse Researchers from Ulsan National Institute of Science and Technology (UNIST) designed a biodegradable, energy efficient artificial synapse that uses a layered structure made from naturally-derived polymers that break down naturally within 16 days in soil. "The device is built like a tiny sandwich, with ion-active layers separated by an ion-binding layer made from cellulose... » read more

Chip Industry Technical Paper Roundup: Jan. 20


New technical papers recently added to Semiconductor Engineering’s library: [table id=515 /] Find more semiconductor research papers here. » read more

Performant Side-Channel Resistant RISC-V Core to Secure Neural Network Inference (Northeastern Univ.)


A new technical paper titled "PermuteV: A Performant Side-channel-Resistant RISC-V Core Securing Edge AI Inference" was published by researchers at Northeastern University. Abstract "Edge AI inference is becoming prevalent thanks to the emergence of small yet high-performance microprocessors. This shift from cloud to edge processing brings several benefits in terms of energy savings, impr... » read more

Chip Industry Week In Review


Space Forge autonomously generated plasma aboard its ForgeStar-1 satellite, utilizing extreme low Earth orbit (LEO) conditions needed for gas-phase crystal growth of wide- and ultra-wide bandgap materials, GaN, SiC, aluminum nitride, and diamonds. Copper prices surged to a historic record of $12,600 per metric ton, an increase of more than 40% YOY, which will impact the cost of data center b... » read more

Chip Industry Week In Review


Deals: NVIDIA inked a $20B non-exclusive licensing deal with Groq for its inference technology. The startup's founder, Jonathan Ross, and some other employees will join NVIDIA to assist in scaling and advancing the technology. The non-exclusive licensing deal, versus an outright purchase, is a tool other companies have used to avoid antitrust regulation. Samsung Ventures made a strategic inv... » read more

Chip Industry Technical Paper Roundup: Oct. 28


New technical papers recently added to Semiconductor Engineering’s library: [table id=486 /] Find more semiconductor research papers here. » read more

Microarchitectural Defense Strategy Against EM Side-Channel Attacks (Northeastern Univ., Binghamton Univ.)


A new technical paper titled "ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors" was published by researchers at Northeastern University and Binghamton University. Abstract "The run-time electromagnetic (EM) emanation of microprocessors presents a side-channel that leaks the confidentiality of the applications running on them. Ma... » read more

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