tag: Nvidia

What’s Next For Transistors And Chiplets
By Mark LaPedus - 21 Oct, 2021 - Comments: 5

Sri Samavedam, senior vice president of CMOS Technologies at Imec, sat down with Semiconductor Engineering to talk about finFET scaling, gate-all-around transistors, interconnects, packaging, chiplets and 3D SoCs. What follows are excerpts of that discussion. SE: The semiconductor technology roadmap is moving in several different directions. We have traditional logic scaling, but packaging i... » read more

Week In Review: Design, Low Power
By Jesse Allen - 15 Oct, 2021 - Comments: 0

Nvidia acquired Oski Technology. Oski provides formal verification methodologies and consulting services, and Nvidia said that the acquisition will allow it to increase its investment in formal verification strategies. Oski's Gurugram, India, design center will become Nvidia's fourth engineering office in the country. Based in San Jose, Calif., it was founded in 2005. Terms of the deal were not... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 15 Oct, 2021 - Comments: 0

Automotive Synopsys and 3D virtual-environment company Dassault Systèmes are collaborating on an automotive lighting system development platform. Synopsys’ optical design tools — LucidShape, LightTools, and CODE V — will be integrated with Dassault Systèmes' 3DEXPERIENCE Platform, which is used by automotive teams from different disciplines to work together on designs and simulations. ... » read more

Blog Review: Oct. 13
By Jesse Allen - 13 Oct, 2021 - Comments: 0

Cadence's Paul McLellan checks out what Google learned in developing multiple generations of its TPU processor, including unequal advancement of logic and memory, the importance of compiler of compatibility, and designing for total cost of ownership. Siemens EDA's Jake Wiltgen argues for the importance of linting as part of eliminating systematic failures in designs complying with ISO 26262.... » read more

Blog Review: Oct. 6
By Jesse Allen - 06 Oct, 2021 - Comments: 0

Arizona State University's Jae-sun Seo and Arm's Paul Whatmough introduce a fully-parallel and fully-pipelined FPGA accelerator for sparse CNNs that can eliminate off-chip memory access and also efficiently support elementwise pruning of CNN weights. Cadence's Paul McLellan highlights trends seen at the recent Hot Chips, from machine learning and advanced packaging driving higher performance... » read more

Software-Hardware Co-Design Becomes Real
By Brian Bailey - 27 Sep, 2021 - Comments: 1

For the past 20 years, the industry has sought to deploy hardware/software co-design concepts. While it is making progress, software/hardware co-design appears to have a much brighter future. In order to understand the distinction between the two approaches, it is important to define some of the basics. Hardware/software co-design is essentially a bottom-up process, where hardware is deve... » read more

Building Complex Chips That Last Longer
By Ed Sperling - 23 Sep, 2021 - Comments: 0

Semiconductor Engineering sat down to talk about design challenges in advanced packages and nodes with John Lee, vice president and general manager for semiconductors at Ansys; Shankar Krishnamoorthy, general manager of Synopsys' Design Group; Simon Burke, distinguished engineer at Xilinx; and Andrew Kahng, professor of CSE and ECE at UC San Diego. This discussion was held at the Ansys IDEAS co... » read more

Data Tsunami Pushes Boundaries Of IC Interconnects
By Ann Mutschler - 22 Sep, 2021 - Comments: 0

Rapid increases in machine-generated data are fueling demand for higher-performance multi-core computing, forcing design teams to rethink the movement of data on-chip, off-chip, and between chips in a package. In the past, this was largely handled by the on-chip interconnects, which often were a secondary consideration in the design. But with the rising volumes of data in markets ranging fro... » read more

Blog Review: Sept. 22
By Jesse Allen - 22 Sep, 2021 - Comments: 0

Ansys' Tyler Ferris describes some of the many ways electronics on a PCB assembly can fail, from component level failures like wirebond breaking and liftoff to board-level failures such as conductive anodic filament failure. Cadence's Paul McLellan considers the switch from low-speed parallel interfaces to high-speed serial interfaces as one of the key advancements making modern data centers... » read more

RISC-V Processor Verification: Case Study
By Imperas - 22 Sep, 2021 - Comments: 0

Abstract: The open RISC-V instruction set architecture is gaining traction with both semiconductor vendors and systems companies. A key question is how to verify the RISC-V processor implementation, especially when developing the RTL and/or adding custom instructions? This paper reports on the techniques used and lessons learned for the verification of a RV64IMACBNSU RISC-V processor by an exp... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy