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Week In Review: Design, Low Power

SemiFive buys Analog Bits; Nvidia’s chiplet interconnect; 3D die stacking data center CPU.

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Design services firm SemiFive acquired Analog Bits, a provider of low-power mixed-signal IP. Analog Bits’ portfolio includes precision clocking macros, I/Os, SerDes, and sensors to monitor PVT. It was founded in 1995 and based in Sunnyvale, California. “Analog Bits has a solid track record of developing and delivering differentiated and high-quality mixed signal IP addressing multiple market segments on various process technologies down to 3nm. This latest acquisition further affirms our vision to provide more enabling technologies with differentiated values to any industry players who wants access to custom silicon,” said Brandon Cho, CEO and founder of SemiFive. Along with full custom design, SemiFive offers a template-based SoC design platform that uses customizable designs and a library of IP to speed design time and reduce cost. This is the Korean company’s first overseas acquisition. Last month, it announced raising $109M in venture funding. Terms of the deal were not disclosed.

Tools, IP, design
Nvidia proposed a way to connect chiplets with its introduction of NVLink-C2C, an ultra-fast chip-to-chip and die-to-die interconnect that will allow custom dies to coherently interconnect to the company’s GPUs, CPUs, DPUs, NICs and SoCs. NVLink-C2C is built on top of Nvidia’s SERDES and LINK design technology, and it is extensible from PCB-level integrations and multichip modules to silicon interposer and wafer-level connections. It supports the Arm AMBA Coherent Hub Interface (AMBA CHI) protocol and will also support the Universal Chiplet Interconnect Express (UCIe) standard. The company says that with advanced packaging, the interconnect would deliver up to 25x more energy efficiency and be 90x more area-efficient than PCIe Gen 5 on Nvidia chips and enable coherent interconnect bandwidth of 900 gigabytes per second or higher.

Microsoft selected Cadence for its part in the Rapid Assured Microelectronics Prototypes (RAMP) Phase II initiative. The RAMP program is a Department of Defense (DoD) initiative to advance secure microelectronics design methods. “Cadence’s participation in the RAMP program brings performance-optimized flows for the DoD’s use on Microsoft Azure,” said Mujtaba Hamid, General Manager, Silicon, Modeling and Simulation, Microsoft. “With this, we established a more comprehensive EDA design environment for the development of advanced microelectronics to facilitate the delivery of new aerospace and defense applications securely and efficiently.”

Cadence’s digital solution on Amazon Web Services (AWS) was qualified by GlobalFoundries for its 22FDX platform. Xenergic noted that it used the Cadence Cloud Passport featuring the digital full flow and the Tensilica Fusion F1 DSP on the GF 22FDX platform to tape out a low-power memory first-time right test chip.

Vestas used Ansys SCADE Model-Based Software Development Environment to implement wind turbine controllers with more integrated safety capabilities to optimize power performance and prevent component damage across the range of wind conditions.

McLaren Strategic Ventures, a business accelerator and investment firm, founded Atlas Silicon, a new custom ASIC design company.

Power devices
Infineon debuted a new family of 650 V silicon carbide (SiC) MOSFETs that aims to offer improved switching behavior at higher currents and 80% lower reverse recovery charge (Q rr) and drain-source charge (Q oss) compared to silicon reference. Available in a compact D 2PAK SMD 7-pin package with .XT interconnection technology, they target high power applications including servers, telecom, industrial SMPS, fast EV charging, motor drives, solar energy systems, energy storage, and battery formation.

Infineon released a new EiceDRIVER 2EDN product family comprised of robust dual-channel low-side 4 A/5 A gate driver ICs. They aim to provide better under-voltage lock-out (UVLO) filtering time, a faster wake-up from UVLO off status and more than two times faster UVLO reaction from start-up and burst mode for fast power MOSFETs as well as wide bandgap switching devices.

Microchip Technology introduced 3.3 kV SiC MOSFETs with RDS(on) of 25 mOhm and Schottky Barrier Diodes (SBDs) with current rating of 90 amps. They are available in die or package form and target electrified transportation, renewable energy, aerospace, and industrial applications.

Diodes Incorporated added a new series of low drop-out (LDO) voltage regulators. The devices have an input voltage range spanning from 5V to 60V, which allows them to be connected to 5V, 9V, 12V, 24V, and 48V rails. They have a quiescent current of 2µA and power supply rejection ratio (PSRR) of 70dB at 1kHz, plus a fast line/load transient response to help mitigate sudden input voltage and load current changes.

Data center, HPC, quantum
AMD introduced a data center CPU using 3D die stacking. The company says the 3rd Gen AMD EPYC processors with 3D V-Cache technology provide up to 66% performance uplift across a variety of targeted technical computing workloads such as computational fluid dynamics (CFD), finite element analysis (FEA), EDA, and structural analysis versus comparable, non-stacked 3rd Gen AMD EPYC processors. In particular, AMD noted that the 16-core EPYC 7373X CPU can deliver up to 66% faster simulations on Synopsys VCS when compared to the EPYC 73F3 CPU. The 3D V-Cache technology bonds the AMD Zen 3 core to the cache module, increasing the amount of L3 while minimizing latency and increasing throughput.

Ansys is upgrading its Ansys Cloud to offer access to AMD EPYC 7003 Series processors with AMD 3D V-Cache on Microsoft Azure HBv3 VMs. Azure said that early tests showed up to 80% improvement in large-scale CFD simulations and up to 50% improvement in explicit FEA crash tests.

Nvidia uncorked an Arm Neoverse-based discrete data center CPU designed for AI infrastructure and high-performance computing. The Nvidia Grace CPU Superchip comprises two CPU chips connected coherently over the NVLink-C2C chip-to-chip interconnect. It has 144 Arm cores, an LPDDR5x memory subsystem, and 1TB/s of memory bandwidth.

Nvidia also debuted its latest Hopper GPU architecture for data center AI applications. Key to the architecture is the Transformer Engine deep learning model, designed to accelerate the training of AI models. According to the company, “Hopper Tensor Cores have the capability to apply mixed FP8 and FP16 precisions to dramatically accelerate AI calculations for transformers. Hopper also triples the FLOPS for TF32, FP64, FP16, and INT8 precisions over the prior generation.” The first GPU based on it, the Nvidia H100, is built on a TSMC 4N process. It supports PCIe Gen5 and HBM3, enabling 3TB/s of memory bandwidth. It also includes numerous features for secure partitioning and confidential computing.

CEA is collaborating with startup C12 Quantum Electronics to produce multi-qubit chips based on carbon nanotubes at wafer scale. The two partners say they have demonstrated the ability to manufacture in volume core components to calibrate, control and read qubits, using standard manufacturing processes. “Quantum technology offers great promise for the next computing generation but still faces significant developmental challenges for fabricating qubit chips. Combining well-established CMOS technologies with C12’s original approach using carbon nanotubes could accelerate progress toward commercializing quantum computing and manufacturing those chips at scale,” said Sébastien Dauvé, CEA-Leti’s CEO. The collaboration will also investigate integration of materials to optimize the properties of qubits hosted in carbon nanotubes, and continued work on the design and fabrication of multi-qubit chips. A final full prototype is expected in 2024.

Read more news at Auto, Security & Pervasive Computing and Manufacturing, Test.

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