tag: Nvidia

What’s In A Node?
By Sundeep Bajikar - 30 May, 2018 - Comments: 0

In an environment where process nodes are no longer consistently delivering the level of improvements predicted by Moore’s Law, the industry will continue to develop “inter-nodes” as a way to deliver incremental improvements in lieu of “full-nodes.” A shift in market requirements, in part due to the rise of AI and IoT, is increasing emphasis on trailing-nodes. When it comes to leading... » read more

Blog Review: May 23
By Jesse Allen - 23 May, 2018 - Comments: 0

Cadence's Paul McLellan digs into the problems of test for 3D ICs s well as new approaches to cell-aware test, modular test and realistic IR drop at CDNLive EMEA. Mentor's Colin Walls shares four more embedded software tips, including always initializing a variable and when to use ++i instead of i++. Synopsys' Taylor Armerding points to a new way that phishing attacks could get around Mic... » read more

Blog Review: May 9
By Jesse Allen - 09 May, 2018 - Comments: 0

Mentor's Doug Amos explains the differences (and similarities) between verification and validation, why switching between engines needs to be simpler, and why the limits of verification are driving a growth in validation importance. Synopsys' Melissa Kirschner provides a primer on 5G and the five technologies that will need to work in tandem to bring the promised high speeds and low latency.... » read more

Challenges At The Edge
By Kevin Fogarty - 03 May, 2018 - Comments: 0

By Kevin Fogarty and Ed Sperling Edge computing is inching toward the mainstream as the tech industry begins grappling with the fact that far too much data will be generated by sensors to send everything back to the cloud for processing. The initial idea behind the IoT/IIoT, as well as other connected devices, was that simple sensors would relay raw data to the cloud for processing throug... » read more

Blog Review: May 2
By Jesse Allen - 02 May, 2018 - Comments: 0

Arm's Greg Yeric looks towards the future of 3D ICs with a dive into transistor-level 3D, including the different proposed methods of stacking transistors, power/performance benefits, and challenges such as parasitic resistance. Mentor's Kurt Takara, Chris Kwok, Dominic Lucido, and Joe Hupcey III explain how a custom synchronizer methodology can help avoid CDC mistakes and errors in FPGA des... » read more

The Week in Review: IoT
By Jeff Dorsch - 27 Apr, 2018 - Comments: 0

Cybersecurity Cybersecurity concerns continued to generate news this week. Symantec reported a corporate espionage hacking campaign against manufacturers of medical supplies, dubbing the efforts “Orangeworm.” The hackers have attacked 24 or more targets this year, and almost 100 since 2015, according to the security software and services firm. Meanwhile, the House Energy and Commerce Co... » read more

Blog Review: Apr. 18
By Jesse Allen - 18 Apr, 2018 - Comments: 0

Cadence's Meera Collier provides an overview of five emerging technologies that could drive the semiconductor industry in the future, from carbon nanotubes to quantum computing. Mentor's Colin Walls reminds embedded software developers of a few common sense tips, including better readability with braces in C/C++ and monitoring stack overflow. Synopsys' Tim Mackey rounds up the last few we... » read more

High-Performance Memory Challenges
By Ann Mutschler - 12 Apr, 2018 - Comments: 1

Designing memories for high-performance applications is becoming far more complex at 7/5nm. There are more factors to consider, more bottlenecks to contend with, and more tradeoffs required to solve them. One of the biggest challenges is the sheer volume of data that needs to be processed for AI, machine learning or deep learning, or even in classic data center server racks. “The design... » read more

Blog Review: Apr. 11
By Jesse Allen - 11 Apr, 2018 - Comments: 0

Mentor's Dennis Brophy looks at how the black box nature of IP means it's hard to tell if a block is free from security risks, even if verification IP and open-source design code can help. Synopsys' Sri Deepti Pisipati explains Panel Self Refresh, a power saving mechanism in Display Port that allows for turning off the video processor and its circuitry when an image is static. Cadence's P... » read more

Choosing The Right Interconnect
By Ed Sperling - 09 Apr, 2018 - Comments: 3

Efforts to zero in on cheaper advanced packaging approaches that can speed time to market are being sidetracked by a dizzying number of choices. At the center of this frenzy of activity is the [getkc id="36" kc_name="interconnect"]. Current options range from organic, silicon and glass interposers, to bridges that span different die at multiple levels. There also are various fan-out approach... » read more

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