tag: Nvidia

The Week In Review: Manufacturing
By Mark LaPedus - 07 Nov, 2014 - Comments: 0

China’s Jiangsu Changjiang Electronics Technology (JCET) has made a bid to acquire STATS ChipPAC for $780 million, according to reports. This year’s top-20 chip ranking includes two pure-play foundries--TSMC and UMC--and six fabless companies, according to IC Insights. GlobalFoundries is forecast to be replaced in this year’s top 20 ranking by fabless IC supplier Nvidia, according to t... » read more

A Decade At The Ceiling
By Barry Pangrle - 05 Nov, 2014 - Comments: 0

This month marks the tenth anniversary of the introduction of the Intel Pentium 4 HT 570J, which had an advertised operating frequency of 3.8 GHz. It was manufactured in a 90nm process, had a VID voltage range of 1.2V-1.425V and was rated at 115W TDP. In a previous article, Power to Fly, we looked at the graph that I’m including again here below for reference. The microprocessor indu... » read more

A Formally Free Lunch
By Brian Bailey - 05 Nov, 2014 - Comments: 0

I am sure many of you can remember the successful events staged by [getperson id="11679" p_name="Eric Hennenhofer"], founder and CEO of [getentity id="22813" comment="Obsidian Software"]. While neither his name nor that of his company may be on the tip of your tongue, DVClub might ring a few more bells. He started it so that he could have a place to meet fellow engineers while enjoying a free l... » read more

The Week In Review: Design
By Ed Sperling - 24 Oct, 2014 - Comments: 0

IP Cadence rolled out a portfolio of stacked die memory verification IP to support Wide I/O-2, Hybrid Memory Cube, high-bandwidth memory, and DDR4-3DS. Included are direct memory access for read, write, save, preload and comparison of memory contents, assertions, error configurability, and a built-in address manager. ARM rolled out additions to its enterprise-class SoC interconnects for qua... » read more

The Week In Review: Design
By Ed Sperling - 08 Aug, 2014 - Comments: 0

Tools Cadence rolled out a custom power integrity tool for dealing with transistor-level electromigration and IR drop with SPICE-level accuracy. It works in conjunction with the company’s existing power integrity tool for cell-level power signoff. Open-Silicon established a high-speed SerDes technology center of excellence to speed design and production of ASICs using high-speed serial co... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 08 Aug, 2014 - Comments: 0

Many are suffering from “fragiphoniphobia” without even realizing it, according to Kyocera. This is the fear of fragile phones and worries about the drops and spills ruining our smartphones and disrupting our lives. A recent survey from comScore revealed that 73% of consumers surveyed rated drop protection or scratch-proof/shatter-proof screens as the most desirable durability feature, whil... » read more

Established Nodes Getting New Attention
By Ed Sperling - 07 Aug, 2014 - Comments: 0

As the price of shrinking features increases below 28nm, there has been a corresponding push to create new designs at established nodes using everything from near-threshold computing to back biasing and mostly accurate analog sensors. The goals of power, performance and cost haven’t changed, but there is a growing realization among many chipmakers that the formula can be improved upon with... » read more

GPUs Dominate (Again) The Green500 List
By Barry Pangrle - 16 Jul, 2014 - Comments: 0

The Green500 has released its latest list of the top 500 most energy-efficient Supercomputers. The top 17 are heterogeneous systems (systems that use more than one type of processor), with the top 15 systems all using NVIDIA Kepler K20 GPUs paired with Intel Xeon CPUs. Still at the top of the list is the Tokyo Institute of Technology GSIC Center’s TSUBAME-KFC, an oil-cooled Kepler powered ... » read more

Five Disruptive Test Technologies
By Mark LaPedus - 19 Jun, 2014 - Comments: 0

For years, test has been a critical part of the IC manufacturing flow. Chipmakers, OSATs and the test houses buy the latest testers and design-for-test (DFT) software tools in the market and for good reason. A plethora of unwanted field returns is not acceptable in today’s market. The next wave of complex chips may require more test coverage and test times. That could translate into higher... » read more

Blog Review: June 18
By Ed Sperling - 18 Jun, 2014 - Comments: 1

Mentor’s Vern Wnek recalls “a living hell” of being trapped in a small office for three weeks with a PCB designer who ate too much garlic and sweated profusely. This could be a reality TV series. What do engineers really think about UVM? Cadence's Richard Goering braved a 7 a.m. breakfast at DAC to hear a panel of experts, including reps from Intel, Ericsson, Imagination and Freescale,... » read more

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