Blog Review: Sept. 18

By Ed Sperling - 18 Sep, 2013 - Comments: 0

By Ed Sperling It’s amazing how irresistible an engineer suddenly becomes when he has an FPGA prototyping board in his hands. Check out the photo of Synopsys’ Mick Posner in Taiwan. Cadence’s Brian Fuller digs into semiconductor startups, why there’s been such a lull, and how new startups are changing. Mentor’s John Day picks out a new product category from TI—inductance to... » read more

HotChips: Power8

By Barry Pangrle - 12 Sep, 2013 - Comments: 2

It’s another year, another HotChips Conference and another update on IBM’s POWER processor. IBM continues to impress with its big iron processor, and this year it’s the new POWER8. IBM announced more details of its new POWER8 processor at HotChips and IBM now joins Intel at 22nm, but with the twist that IBM’s process is based on SOI technology. The POWER8 quadruples the thread count ... » read more

Power Shifts In Digital Chip Space

By Bhanu Kapoor - 08 Aug, 2013 - Comments: 0

By Bhanu Kapoor The power issue has been quite disrupting in the digital semiconductor space. The processor architecture shifted to parallel processing with the “power wall” stopping the frequency scaling that the industry had conveniently used in the last few decades. The power issue also is causing semiconductor process technology to change in ways other than simply scaling from one ... » read more

Material Impact

By Barry Pangrle - 08 Aug, 2013 - Comments: 0

Ed Sperling’s June article New Approaches to Better Performance and Lower Power took a look at the new materials that researchers are examining for future technology nodes. Figure 1. Basic Planar CMOS FET Figure 1 shows a basic diagram of a planar CMOS FET (diagrams for other FETs can be found here). The drive strength of a FET is proportional to , where μ is the surface mobility for... » read more

GPUs May Speed UP EDA Algorithms

By Ann Mutschler - 25 Jul, 2013 - Comments: 1

The sequential EDA algorithms of old cannot keep pace with increasing design complexity, which is driving the industry to look at parallelism and other computational architectures such as the graphical processing unit (GPU). A 10X or 20X speedup for gate-level simulations means that a test that runs today in a week will run in less than a day, and a test that runs today in a month will run i... » read more

The Green500 And The Charge Towards Exascale Computing

By Barry Pangrle - 11 Jul, 2013 - Comments: 0

The latest Green500 list (Excel spreadsheet here) was just released at the end of June, and heterogeneous systems continue to dominate the top of the list with the new leader besting the old by nearly 30%. Two systems using Intel Xeon E5-2687W 8-Core 3.1 GHz processors coupled with NVIDIA K20’s topped the list. Eurotech’s Eurora and Aurora Tigon both broke the 3,000 MFLOPS/W barrier, record... » read more

Life After Smartphones

By Frank Ferro - 27 Jun, 2013 - Comments: 0

By Frank Ferro Don’t let the title confuse you. Smartphones are not going away anytime soon. In fact this year’s smartphone shipments have exceeded feature phones for the first time, with a total of 216 million units in Q1, according to IDC, and the overall mobile phone market is expected to grow 4.3% in 2013. This volume represents an increase in smartphone sales of 42% from Q1 2012. ... » read more

Faster Assembly Required

By Ed Sperling - 27 Jun, 2013 - Comments: 0

Speeding up production has been a mantra dating back throughout recorded history, and presumably well before that. That’s what technology was created for—roads, bridges aqueducts, computers, the Internet, and everything that connects the real to the virtual world. A speech by Nvidia chief scientist Bill Dally at DAC that complex SoCs should only take a couple weeks to design by two guys ... » read more

Automotive Power Concerns

By Ed Sperling - 13 Jun, 2013 - Comments: 0

By Ann Steffora Mutschler With advanced semiconductor technologies infiltrating the automotive market in ever new and exciting ways, there are also challenges to implementation involving power. In fact, power has become a concern in many areas of automotive design. Consider the Tesla, for example. The dashboard features a 17” touchscreen with the entire vehicle controls. This system i... » read more

New Standard!

By Barry Pangrle - 13 Jun, 2013 - Comments: 0

It’s been a little over four years since the first IEEE 1801 standard was officially published in March 2009, but the standard can trace its roots back to years before that date. On May 30th, the IEEE released a press announcement for the newest version of the standard, IEEE 1801-2013 (a.k.a. UPF 2.1). It takes a considerable amount of effort and attention to detail to produce a solid standar... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?