The Week In Review: Design

Cadence adds power integrity tool; Open-Silicon launches SerDes design center; Calypto wins Olympus deal; Rambus wins Microsemi security deal; Samsung joins OpenPOWER; ARM wraps up Duolog buy.


Cadence rolled out a custom power integrity tool for dealing with transistor-level electromigration and IR drop with SPICE-level accuracy. It works in conjunction with the company’s existing power integrity tool for cell-level power signoff.

Open-Silicon established a high-speed SerDes technology center of excellence to speed design and production of ASICs using high-speed serial communications. The goal is to enable networking up to 100G.

Calypto won a deal with Olympus, which will use Calypto’s high-level synthesis platform for advanced ASIC design. Olympus said HLS shortened design time for beginning designers and allowed them to generate complex IP quickly.

Microsemi extended its license of Cryptography Research’s differential power analysis for secure booting of its FPGAs. The license will apply to third-party MCUs, DSPs, GPUs and FPGAs used in the same system. Cryptography Research is owned by Rambus.

Samsung Electronics joined the OpenPOWER Foundation, which was created by IBM, Google, Mellanox, Nvidia and Tyan last year to build advanced server, networking, storage and GPU acceleration technology for next-generation hyperscale and cloud computing. The alliance is based on IBM’s POWER architecture.

ARM completed its acquisition of Duolog Technologies. The deal, which was announced in May, bolsters ARM’s tools for subsystem functional verification and validation.

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