The Good And Bad Of Chiplets

By Mark LaPedus - 27 May, 2020 - Comments: 1

The chiplet model continues to gain traction in the market, but there are still some challenges to enable broader support for the technology. AMD, Intel, TSMC, Marvell and a few others have developed or demonstrated devices using chiplets, which is an alternative way to develop an advanced design. Beyond that, however, the adoption of chiplets is limited in the industry due to ecosystem issu... » read more

Die-to-Die Interconnects for Chip Disaggregation

By Mondeep Thiara - 10 Nov, 2018 - Comments: 0

Today, data growth is at an unprecedented pace. We’re now looking at petabytes of data moving into zettabytes. What that translates to is the need for considerably more compute power and much more bandwidth to process all that data. In networking, high-speed SerDes PHYs represent the linchpin for blazing fast back and forth transmission of data in data centers. In turn, demand is increa... » read more

Die-To-Die Interconnects For Chip Disaggregation

By Mondeep Thiara - 09 Nov, 2018 - Comments: 0

SerDes For Chiplets

By Jeff McGuire - 16 Oct, 2018 - Comments: 0

The XSR 56G and 112G Interoperability Agreements (IAs) announced by the OIF are intended to cover a channel consisting of a pair of up to 50mm. The primary defined application of the XSR SerDes is connecting a chip to a “nearby” optical engine. Because the requirements on these channels are much less stringent than they are on long reach channels, XSR SerDes are expected to have lower power... » read more

Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: OIF

The Good And Bad Of Chiplets

Die-to-Die Interconnects for Chip Disaggregation

Die-To-Die Interconnects For Chip Disaggregation

SerDes For Chiplets

Trending Articles

NAND Flash Targets 1,000 Layers

One Chip Vs. Many Chiplets

FOPLP Gains Traction in Advanced Semiconductor Packaging

HBM Options Increase As AI Demand Soars

Asia Government Funding Surges

Knowledge Centers
Entities, people and technologies explored