The Case For Embedded FPGAs Strengthens And Widens

By Brian Bailey - 25 Apr, 2019 - Comments: 2

The embedded FPGA, an IP core integrated into an ASIC or SoC, is winning converts. System architects are starting to see the benefits of eFPGAs, which offer the flexibility of programmable logic without the cost of FPGAs. Programmable logic is especially appealing for accelerating machine learning applications that need frequent updates. An eFPGA can provide some architects the cover they ne... » read more

Safety-Critical Coverage

By Ed Sperling - 24 Apr, 2019 - Comments: 0

Dave Landoll, solutions architect at OneSpin Solutions, discusses verification in safety-critical designs, why it’s more of a challenge in automotive than in avionics, and why verification of these systems includes what the system should not be doing as well as what it should be doing. https://youtu.be/Ze3WwEARfx0 » read more

The Role Of EDA In AI

By Brian Bailey - 17 Apr, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the role that EDA has in automating artificial intelligence and machine learning with Doug Letcher, president and CEO of Metrics; Daniel Hansson, CEO of Verifyter; Harry Foster, chief scientist verification for Mentor, a Siemens Business; Larry Melling, product management director for Cadence; Manish Pandey, Synopsys fellow; and Raik Brinkmann, CEO ... » read more

Optimization Challenges For Safety And Security

By Brian Bailey - 11 Apr, 2019 - Comments: 0

Complexity challenges long-held assumptions. In the past, the semiconductor industry thought it understood performance/area tradeoffs, but over time it became clear this is not so simple. Measuring performance is no longer an absolute. Power has many dimensions including peak, average, total energy and heat, and power and function are tied together. Design teams are now dealing with the impl... » read more

From AI Algorithm To Implementation

By Brian Bailey - 10 Apr, 2019 - Comments: 0

The Long And Detailed Road To Automotive Compliance

By Ann Mutschler - 04 Apr, 2019 - Comments: 0

Compliance with automotive safety requirements is slowing down both innovation and participation by a flurry of startups as the whole ecosystem struggles to bring autonomous vehicles to reality. This is particularly onerous for chipmakers, which face a high bar for IC integrity and reliability. They must meet specifications and be free of design errors. Improper behavior in corner-case s... » read more

Fibonacci And Honey Bees Have Something In Common: A Sweet Spot For Formal

By Sergio Marchese - 28 Mar, 2019 - Comments: 0

Time flies and the OneSpin’s Holiday Puzzle tradition has reached its third year. In December 2016, OneSpin challenged engineers everywhere to solve the Einstein riddle using assertions and a formal verification tool. In December 2017, the challenge was to model the hardest Sudoku in the world using assertions and find a solution with a formal tool. In addition, participants had to prove that... » read more

Utilizing More Data To Improve Chip Design

By Ann Mutschler - 28 Mar, 2019 - Comments: 0

Just about every step of the IC tool flow generates some amount of data. But certain steps generate a mind-boggling amount of data, not all of which is of equal value. The challenge is figuring out what's important for which parts of the design flow. That determines what to extract and loop back to engineers, and when that needs to be done in order to improve the reliability of increasingly com... » read more

The Automation Of AI

By Brian Bailey - 28 Mar, 2019 - Comments: 0

Billion-Gate Design Connectivity

By Ed Sperling - 27 Mar, 2019 - Comments: 0

Sasa Stamenkovic, senior field application engineer at OneSpin Solutions, explains how to find and resolve connectivity issues in integrating large numbers of components in very big designs, often at the leading edge nodes and in markets such as AI. » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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