The Case For Embedded FPGAs Strengthens And Widens

Combining the flexibility of a FPGA with the performance and cost benefits of an SoC is pushing this technology well into the mainstream.


The embedded FPGA, an IP core integrated into an ASIC or SoC, is winning converts. System architects are starting to see the benefits of eFPGAs, which offer the flexibility of programmable logic without the cost of FPGAs.

Programmable logic is especially appealing for accelerating machine learning applications that need frequent updates. An eFPGA can provide some architects the cover they need to launch products they know will need frequent updating.

Field programmable gate arrays (FPGAs) traditionally were considered too expensive for most applications and often relegated to prototypes or providing a time-to-market advantage for emerging standards. But the economics are changing. Integrating a reprogrammable fabric into an SoC is increasingly seen as a viable and valuable option.

“With an eFPGA, you define the quantity of look-up-tables (LUTs), registers, embedded memory, and DSP blocks. You can also control the aspect ratio, number of I/O ports, making tradeoffs between power and performance,” says Kent Orthner, systems architect at Achronix. “At the same time, the industry is embracing heterogeneity. You need different blocks that are good for different things. So you may have a secure block, and this is a place where eFPGAs play well. They can be specialized, but you don’t have to keep it that way.”

Fig. 1: SoC with programmable acceleration. Source: Achronix

That changes the economics of FPGA technology. “For many years [programmable logic] was very expensive,” says Joe Mallett, senior product marketing manager for FPGA-based synthesis software tools at Synopsys. “The cost per LUT was high, and to get a usable amount of combinational logic on the silicon was too expensive. The inflection point was somewhere around 40nm, and then the cost per LUT became low enough that you can put enough logic on the SoC or ASIC that it makes sense.”

It has been more than a decade since 40nm was first introduced. “It takes time between when architects have a new tool to consider and manage to wrap their heads around it,” says Geoff Tate, CEO at Flex Logix. “Five years ago, embedded FPGA became available. [Architects] never had the opportunity to think about it before then. Over time, with education and understanding, and demonstration that the technology is viable and ready for production, we are seeing architects figuring out how to make best use of the embedded FPGA.”

Several characteristics and trends make eFPGAs appealing now:

  1. Product flexibility is seen as the primary application, and the need for this is increasing now that migration to new nodes is slowing.
  2. An algorithm mapped into an FPGA fabric can outperform many other processing options while remaining upgradeable.
  3. Integration reduces parts count and thus costs.
  4. Integration provides additional security and adds flexibility to deal with future threats.
  5. eFPGAs can extend product life or enhance business models by being able to upgrade products in the field.
  6. A new type of microcontroller that includes an FPGA fabric may be an option in the future.

Product flexibility
Few people claim that the traditional Moore’s Law still applies to most product development. “For a significant number of designs, you don’t need all of the advances of 7nm,” says Frank Schirrmeister, senior group director for product management and marketing at Cadence. “For them, the lesser nodes may be sufficient, and with that the flexibility of an FPGA embedded into an SoC is good.”

The programmability of eFPGAs enables IC functionality to be changed on the fly after chip development is complete. “This enables a single IC to address a diverse set of use cases and adapt to changing requirements instead of forcing development of another ASIC,” adds Brian Mathewson, verification technologist for Mentor, a Siemens Business. “Incorporating a programmable logic fabric may have a penalty in terms of power, performance and design cost compared with the same logic implemented in traditional gates. This drives a tradeoff between cost and flexibility for a target application.”

But sometimes traditional gates make little sense. “If we consider serial I/O, there are many relevant standards and people would like to have the flexibility to implement all of them,” says Flex Logix’s Tate. “But you don’t have to have the entire serial I/O go into eFPGA. Large portions of it remain the same for all of the standards.”

Fig. 2: Flex Logix’s inferencing chip architecture with reconfigurable data path.

Tobias Welp, engineering manager for OneSpin Solutions, agrees. “Programmable I/O is a popular application. In addition to product variations, it fosters the use of new interface standards that may still have issues to be resolved and additional features planned for future revisions.”

Increasing market size makes good sense. “Markets that are fragmented, and thus have modest unit volumes, are well suited for eFPGA deployment as a single SoC can target multiple use cases by customizing the logic on the eFPGA,” says Himanshu Sanghavi, senior director of engineering for programmable IP for Quicklogic. “One such a market is IoT. While the total market is very high volume, many sub-segments are within the umbrella of IoT, ranging from home automation to wearable devices to a variety of smart sensors. Each of these segments has specific requirements that are different from use cases in the other segment(s).”

Machine learning is adding some new requirements into products. “FPGA fabric may be added to SoCs to enable variations in the engines and processors with domain-specific instruction sets,” points out OneSpin’s Welp. “In some cases, it may be possible to map algorithms for machine learning and other key applications into hardware and later refine the design as the results improve.”

SoC designers are constantly evaluating performance and flexibility tradeoffs between competing solutions for their application. “On one end of the spectrum, general-purpose programmable processors offer the greatest amount of flexibility via software, while at the other end of the spectrum, custom fixed-function blocks designed in RTL offer the best power/performance characteristics,” says Quicklogic’s Sanghavi. “FPGAs sit somewhere in between, offering better power/performance than a general-purpose CPU, and more flexibility than fixed function RTL. As a result, embedded FPGAs are most suitable for SoC design tasks, for which some amount of post-silicon programmability is a must, yet a pure software solution does not meet the performance or power goals of the application.”

Reduced integration costs
Mainstream FPGA providers have been integrating increasing amounts of functionality into their devices for a long time, making them SoCs with a large amount of reprogrammable fabric. “FPGA vendors now offer high-end devices that fully qualify as SoCs, including CPUs, specialty engines and large memories,” says Welp. “Conversely, SoC developers now have the ability to embed FPGA fabric into their designs to provide a high level of flexibility. Either type of chip can be called a heterogenous computing platform with a rich mixture of fixed processors, programmable engines, programmable logic and memory.”

But there is an important difference. “Traditional FPGAs had some high-level fixed blocks and they were expecting the customer to be able to use some of those,” says Yoan Dupret, managing director and vice president of business development for Menta, an embedded programmable logic company. “The major difference between FPGAs and embedding an FPGA fabric into an SoC is that you don’t consider it a blank sheet of paper where you can do whatever you want with the eFPGA. One way to improve power/performance/area (PPA) tradeoffs is to restrict the architectures that you will use, and that is not hard because your ASIC or SoC is already restricting the number of applications that they will have.”

Security is becoming an increasing concern for connected products. “The eFPGA allows developers to have the flexibility to do things such as to change security protocols and adapt their chips to changing markets and customer needs,” says Tate. “Given how expensive it is to design a chip, anything you can do to extend the chip’s useful life, and breadth of application will improve your return on investment.”

This is particularly important in applications where chips are expected to last a decade or more, such as in automotive or industrial markets. Security measures implemented today will likely not be considered as secure in a decade.

Extended life, changing economics
Product life can also be extended for deployed products. “The flexibility of the eFPGA helps extend the time-in-market for the SoC, as new use cases that become known well after the SoC has gone into production can be addressed through the use of the eFPGA,” says Sanghavi. “The embedded FPGA provides area, power and cost benefits over the two-chip solution.”

This may enable new business models to be developed such that additional capabilities could be added to deployed products, changing the business model from a pure sales model to a service model.

In addition, eFPGAs can have a fundamental impact on the entire design process. Rather than developing another chip with new IP, the same chip can be updated or even applied to new markets.

“The cost of derivatives is becoming more important as the cost of developing chips goes up,” says Achronix’s Orthner. “You want to get as much bang for your buck. This allows you to spread the NRE for an ASIC across a multitude of different functions and markets. You can develop one chip and sell it as a dozen different parts.”

This approach can span everything from SoCs to microcontrollers, which have long been used for products that require software flexibility.

“Today, almost all our customers program the FPGA themselves,” says Tate. “If you are going to build and sell a chip where the customer will program it, it opens up a bunch of support and business questions. Companies want to build a chip where they do the programming, to make sure they fully understand all of the issues in the hardware and software and where they can control everything first. Then they can look at the next step, which is letting the customers program it.”

Architectural considerations
Integrating an eFPGA fabric can be done in several ways, but careful consideration has to be given to the intended application. “There are two primary integration types,” says Synopsys’ Mallett. “One is being used as an accelerator and can do some heavy lifting in processing and the other is more of potential bugs fixes or silicon configuration or secret sauce that will not become publicly visible. These are different use cases for the eFPGA. For heavy acceleration, where it will be used for accelerating functionality, it is closer to the idea of the standalone chips with an embedded processor, but with a smaller fabric amount.”

Without due consideration, integration may lead to disappointing results. “Architects need to understand the tradeoffs and how to get the most advantage out of an eFPGA with the least penalty,” says Tate. “People start thinking about how great it is to have flexibility, but then they try to take a giant block of the chip and put it into an eFPGA. They end up finding that it is too big and expensive. The architects have to figure out how to use it. They must examine the RTL and figure out which portions need to be flexible and which portions can remain in hardwired logic. They have to partition the architecture, which takes some work and thinking about. They should put as little as possible of their architecture into flexible eFPGA in order to minimize the area cost, but still get the required amount of flexibility.”

Sizing of the fabric is critical. “There are a couple of different ways to approach this problem,” says Sanghavi. “If the SoC designer has a good idea of the hardware they plan to map to the embedded FPGA, they can use the tools provided by the vendor to decide on the size of the fabric. Alternatively, in many instances SoC designers are using an embedded FPGA because they are not sure what hardware will need to go on it over the life of the IC, and there is the need to amortize the high SoC design cost across multiple system designs. In this situation, it is best to use the largest eFPGA that will still meet the die size budget of the SoC. The larger the fabric, the more post-silicon flexibility it will provide.”

That can be a fine line. “eFPGAs can vary in size depending on the function they are serving,” adds Mentor’s Mathewson. “Additional flexibility built into today’s SoCs can always be useful, but there are impacts to building this flexibility in. It is critical to bound your potential design space up front.”

This will vary depending upon the end market. “If you look at the person who has an FPGA with fixed components around it, you have specific product categories, such as a large device with lots of FPGA, because you have video and processing pieces to be mapped into it, whereas others may have a smaller FPGA portion,” says Cadence’s Schirrmeister. “You figure out for the FPGA how much data access you need to provide the I/O bandwidth, you figure out the processing need, and that determines speed and size. And you do this with some example applications.”

The problem is similar to sizing memory for software. “You can never have enough software memory, but that doesn’t mean you can afford what you may like,” says Tate. “We provide tools that can determine, for various RTL, how big the array needs to be and how fast it will run. Then they have to make a judgment, because you never know what may happen in the future and how much bigger my RTL might become.”

What judgment do people use today? “Once a customer has worked out what they need for a handful of representative applications, then can size the resources they require,” says Menta’s Dupret. “They might increase those resources by a fixed amount. Some might go with 10% while other may go up to 50%. It is really a guess today.”

Power management
Power reduction is important, but when considering a flexible resource such as eFPGA, it becomes even more difficult. “All transistors leak unless you put in power gating, which also has a cost,” says Tate. “For some applications, typically 40nm and above, power is very critical, and they are looking to include a power-gating function. Generally, at 28nm and 16nm, people are more focused on speed, and power gating cuts into performance.”

Power gating also leads to synthesis complications. “When you look at SoCs, you have the ability to turn on and off blocks depending on usage needs,” says Mallett. “There is a lot more independent power control. When you combine FPGA into an SoC, it is likely to be turned on and off, programmed and reprogrammed, so you have to be aware of those possibilities. You have to be aware of how you are programming the block and how it relates to the system. For synthesis, I may have multiple power domains in an FPGA that I need to take care of and know what that means. That may change the way I am doing the design because if you cross power domains, you have to make sure that the right pieces are powered up.”

The important tradeoff is the amount of energy consumed for a specified function. “When you are working on an application that is very sensitive to power consumption, like an IoT application, the size of the eFPGA is usually much smaller and the number of applications it is to be used for is more limited,” says Dupret. “They don’t need to have as much expansion room. But on the other side, architects must get out of the mindset that eFPGA will always take a lot of space and power, because there may be a lot of instances where this is not the case. It may even be more area-efficient or power-efficient than other solutions.”

This adds a level of complexity to product development. “As integration continues to increase, programming models become more complex,” says Max Odendahl, CEO at Silexica. “Engineers now need to consider how the application is distributed across the processing elements and FPGA fabric and know how to program each element. System-level memory dependencies and cache coherency must also be considered in the design process. EDA tool vendors will need to keep pace and provide utilities that help simplify the programming model.”

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Endric Schubert / Missing Link Electronics says:

Nice article, Brian, please continue covering this field!

Two decades ago, IBM (and others) announced adding programmable logic to their ASIC but gained little traction. Maybe this time the need to implement Domain-Specific Architectures for performance scaling is strong enough to make eFPGA a success.

At Missing Link Electronics we certainly see a need for programmable logic in autonomous driving and elsewhere.

Brian Bailey says:

Thanks Endric. It is funny how many times technology has been before its time. Both the technology and the application have to be present to make something a business success.

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