Uncertainty Rocks Chip Market

By Ed Sperling - 30 Jun, 2016 - Comments: 1

The semiconductor industry is undergoing sweeping changes in every direction, making it far more difficult to figure out which path to take next, when to take it, and how to get there. The next few years will redefine which semiconductor companies emerge as leaders, which ones get pushed down or out or absorbed into other companies, and which markets will be the most lucrative. And that coul... » read more

Achieving 100% Functional Coverage By Operational Assertion-Based Verification

By OneSpin Solutions - 29 Jun, 2016 - Comments: 0

This white paper presents Operational Assertion-Based Verification (ABV), an advanced formal verification methodology resulting in a predictable, small number of high-level assertions capturing the functionality of a design. Operational ABV enables an automatic formal coverage analysis, which identifies holes in verification plans, unverified design functionality as well as errors and omissio... » read more

Open Standards For Verification?

By Ann Mutschler - 01 Jun, 2016 - Comments: 0

The increasing use of verification data for analyzing and testing complex designs is raising the stakes for more standardized or interoperable database formats. While interoperability between databases in chip design is not a new idea, it has a renewed sense of urgency. It takes more time and money to verify increasingly complex chips, and more of that data needs to be used earlier in the fl... » read more

Do Single-Vendor Flows Make Sense Yet?

By Ann Mutschler - 26 May, 2016 - Comments: 0

For many years in the EDA industry, there has been talk of a complete design tool flow from a single vendor, and each of the main EDA players is capable of offering one. But whether they actually do — or should — is an interesting discussion. There are obvious pros and cons on the technical side. But it is the business and marketing issues that are really at the crux of the debate today.... » read more

Going Open Source

By Dave Kelf - 26 May, 2016 - Comments: 2

Open Source often is thought of as an alternative to commercial software licensed using fairly typical business models. For example, variants of open source Linux supplied by companies such as Red Hat charge a subscription for support and maintenance. Maybe there is an opportunity to leverage Open Source alongside commercial EDA software to provide use model advantages and open development f... » read more

Capturing Timing Diagrams In Operational SVA

By OneSpin Solutions - 25 May, 2016 - Comments: 0

Timing diagrams provide an excellent, intuitive starting point for writing assertions to capture the intended behavior of designs. However, the standard assertion languages SVA and PSL do not provide direct constructs for capturing timing diagrams. This white paper presents Operational SVA – a simple yet powerful SVA library – which allows to develop assertions directly from timing diagrams... » read more

Grappling With IoT Security

By Ed Sperling - 09 May, 2016 - Comments: 1

By Ed Sperling & Ernest Worthman As the IoT begins to take shape, the security implications of connecting devices and systems to the Internet and what needs to be done to secure them are coming into focus, as well. There is growing consensus across the semiconductor industry that many potential security holes remain, with new ones surfacing all the time. But there also is widespread r... » read more

ESL Flow is Dead

By Brian Bailey - 28 Apr, 2016 - Comments: 3

It was 20 years ago that Gary Smith coined the term [getkc id="48" comment="Electronic System Level"] (ESL). He foresaw the next logical migration in abstraction up from the [getkc id="49" comment="Register Transfer Level"] (RTL) to something that would be capable of describing and building complex electronic systems. He also saw that the future of EDA depended upon who would control that marke... » read more

Way Too Much Data

By Ed Sperling - 28 Apr, 2016 - Comments: 0

Moving to the next process nodes will produce volumes more data, forcing chipmakers to adopt more expensive hardware to process and utilize that data, more end-to-end methodologies, as well as using tools and approaches that in the past were frequently considered optional. Moreover, where that data needs to be dealt with is changing as companies adopt a "shift left" approach to developing so... » read more

Formal Verification Applied To The Renesas MCU Design Platform Using OneSpin Tools

By OneSpin Solutions - 27 Apr, 2016 - Comments: 0

An effective measure of verification progress, together with guidance towards design areas remaining untested, requires a precise view of the test coverage achieved. To risk signing off the verification process without understanding the quality of testing raises the specter of post-production device bugs. OneSpin Solution’s patented Quantify technology employs Observation Coverage, which eval... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.