tag: Onto Innovation

Adaptive Shot Technology To Address Severe Lithography Challenges For Advanced FOPLP
By Onto Innovation - 07 Dec, 2020 - Comments: 0

Fan-out wafer level packaging (FOWLP) is a popular new packaging technology that allows the user to increase I/O in a smaller IC size than fan-in wafer level packaging. Market drivers such as 5G, IoT, mobile and AI will all use this technology. According to Yole Développement’s analysis, the fan-out packaging market size will increase to $3 billion in 2022 from $2.44 hundred million in 2014,... » read more

Defect Challenges Grow For IC Packaging
By Mark LaPedus - 22 Oct, 2020 - Comments: 0

Several vendors are ramping up new inspection equipment based on infrared, optical, and X-ray technologies in an effort to reduce defects in current and future IC packages. While all of these technologies are necessary, they also are complementary. No one tool can meet all defect inspection requirements. As a result, packaging vendors may need to buy more and different tools. For years, p... » read more

The Next Advanced Packages
By Mark LaPedus - 18 Jun, 2020 - Comments: 4

Packaging houses are readying their next-generation advanced IC packages, paving the way toward new and innovative system-level chip designs. These packages include new versions of 2.5D/3D technologies, chiplets, fan-out and even wafer-scale packaging. A given package type may include several variations. For example, vendors are developing new fan-out packages using wafers and panels. One is... » read more

What’s Next With AI In Fabs?
By Mark LaPedus - 22 Apr, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss the issues and challenges with machine learning in semiconductor manufacturing with Kurt Ronse, director of the advanced lithography program at Imec; Yudong Hao, senior director of marketing at Onto Innovation; Romain Roux, data scientist at Mycronic; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. Part one ... » read more

Metrology Challenges For Gate-All-Around
By Mark LaPedus - 16 Apr, 2020 - Comments: 3

Metrology is proving to be a major challenge for those foundries working on processes for gate-all-around FETs at 3nm and beyond. Metrology is the art of measuring and characterizing structures in devices. Measuring and characterizing structures in devices has become more difficult and expensive at each new node, and the introduction of new types of transistors is making this even harder. Ev... » read more

How And Where ML Is Being Used In IC Manufacturing
By Mark LaPedus - 01 Apr, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss the issues and challenges with machine learning in semiconductor manufacturing with Kurt Ronse, director of the advanced lithography program at Imec; Yudong Hao, senior director of marketing at Onto Innovation; Romain Roux, data scientist at Mycronic; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. Part one ... » read more

What Machine Learning Can Do In Fabs
By Mark LaPedus - 25 Mar, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss the issues and challenges with machine learning in semiconductor manufacturing with Kurt Ronse, director of the advanced lithography program at Imec; Yudong Hao, senior director of marketing at Onto Innovation; Romain Roux, data scientist at Mycronic; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. L-R:... » read more

Finding Defects In IC Packages
By Mark LaPedus - 17 Dec, 2019 - Comments: 0

Several equipment makers are ramping up new inspection equipment to address the growing defect challenges in IC packaging. At one time, finding defects in packaging was relatively straightforward. But as packaging becomes more complex, and as it is used in markets where reliability is critical, finding defects is both more difficult and more important. This has prompted the development of a ... » read more

Planning For Panel-Level Fan-out
By Mark LaPedus - 21 Nov, 2019 - Comments: 0

Several companies are developing or ramping up panel-level fan-out packaging as a way to reduce the cost of advanced packaging. Wafer-level fan-out is one of several advanced packaging types where a package can incorporate dies, MEMS and passives in an IC package. This approach has been in production for years, and is produced in a round wafer format in 200mm or 300mm wafer sizes. Fan-out... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 18 Oct, 2019 - Comments: 0

Chipmakers The semiconductor capital spending race continues to escalate in the leading-edge logic space. Intel and Samsung have separately announced big capital spending plans in 2019. Intel’s latest CapEx budget is $15.5 billion in 2019, while Samsung’s CapEx is slated for $16.204 billion for the year, according to KeyBanc Capital Markets. Now, TSMC is raising the stakes. TSMC this... » read more

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