Metrology Challenges For Gate-All-Around

Why future nodes will require new equipment and approaches.


Metrology is proving to be a major challenge for those foundries working on processes for gate-all-around FETs at 3nm and beyond.

Metrology is the art of measuring and characterizing structures in devices. Measuring and characterizing structures in devices has become more difficult and expensive at each new node, and the introduction of new types of transistors is making this even harder. Even though gate-all-around FETs are considered an evolutionary step from finFETs, with a boost in performance, they are expensive and difficult to make.

Any new technology is prone to defects, and this is where metrology fits in. All device makers use various metrology equipment to pinpoint problems in devices and processes, which in turn boosts yield.

At advanced nodes, the challenges have been growing for some time. Leading-edge devices are more complex with smaller features, which makes them harder to measure. Chipmakers require several different metrology tool types, including electron-beam, optical and X-ray. Unfortunately, no tool can handle all requirements.

Moving to a new transistor type presents even more challenges. For example, foundries are developing one type of gate-all-around technology called nanosheet FETs. A related transistor is called a nanowire. Both are more complex with smaller dimensions than finFETs. “We see a trend of continuing to advance chip architectures in the third dimension. We see new types of transistors for better performance. Gate-all-around is the most known one,” said Efi Megged, director of product marketing at KLA. “With new chip technologies, we also have new materials, which pose new challenges. For example, you have ruthenium and cobalt, as well as new types of resists for EUV scanners.”

With those issues in mind, gate-all-around requires an assortment of advanced metrology tools. “The big challenges associated with metrology for manufacturing nanosheet and nanowire FETs include new processes, sub-surface 3D features and aggressive pitches,” said Alain Diebold, Special Assistant to the President and the Empire Innovation Professor of Nanoscale Science at SUNY Polytechnic Institute. “The goal is to enable non-destructive measurements that can be used for process monitoring.”

Fortunately, the existing advanced metrology tools can be deployed for gate-all-around. New techniques also are being developed. But there are some gaps, and solutions to fill those gaps aren’t ready. Moreover, all of the tools are expensive.

Figure 1: Planar transistors vs finFETs vs nanosheet FET. Source: Samsung

Measuring finFETs
Before understanding gate-all-around and the metrology solutions involved, it’s important to understand how metrology has evolved in the current transistor types, namely planar and finFETs.

A chip incorporates a multitude of transistors. A transistor, which acts like a switch in a device, consists of a source, gate, and drain. In operation, current flows from the source to a drain, and the flow is controlled by the gate.

At 28nm and above, chips consist of planar transistor structures with large features. For this, metrology is a straightforward process. Chipmakers use a handful of metrology systems, such as CD-SEMs and ellipsometers, to measure the structures.

The critical-dimension scanning electron microscope (CD-SEM), the workhorse metrology tool in fabs, takes top-down measurements of structures. Ellipsometry utilizes polarized light to characterize structures.

The big change occurred at 20nm, when planar transistors hit the wall and encountered short-channel effects. In response, Intel in 2011 moved to finFETs at 22nm. Foundries moved to finFETs at 16nm/14nm.

Fig. 2: FinFET vs. planar. Source: Lam Research

In finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin. “The greater surface area between gate and channel provides better control of the electric field and thereby reduces leakage in the ‘off’ state,” said Nerissa Draeger, director of university engagements at Lam Research, in a blog. “The result is a transistor with better performance and reduced power consumption.” FinFETs are also more expensive to manufacture, and they are more difficult to measure because they incorporate three-dimensional structures with smaller features. As a result, finFETs require both two- and three-dimensional measurements.

In a 28nm planar device, for example, a given transistor may have a 117nm to 120nm contacted gate pitch (CPP) and a 90nm metal pitch, according to WikiChip. CPP, a key transistor metric, measures the distance between a source and drain contact.

In comparison, TSMC’s 7nm finFET has a 57nm-64nm CPP and a 40nm metal pitch, according to WikiChip. TSMC’s upcoming 5nm finFET will have a 48nm CPP and a 30nm metal pitch, according to the website.

TSMC is expected to extend the finFET to 3nm, which presents several challenges in the fab. In a simple finFET process, fin-like structures are processed on a substrate using a self-aligned double/quadruple (SADP/SAQP) patterning process. Each fin has a distinct width, height and shape.

At times, the process can cause variations between the distances of the fins, which is sometimes called pitch walking. This can impact device performance.

This, in turn requires, more critical dimension (CD) measurements. Planar transistors require five to six measurements. FinFETs require 12 or more CD measurements, such as the gate height, fin height, fin width and sidewall angle.

For this, chipmakers use CD metrology tools, such as CD-SEMs, optical CD (OCD) systems and others. “What’s been in the literature for quadruple spacer patterning is doing a combination of scatterometry and CD-SEM,” SUNY’s Diebold said. “The CD-SEM pins down the three different spacings and it puts that into the software for determining the scatterometry results. Along the way, you also have to do some basic TEM work.”

As stated, CD-SEMs take top-down images. It also requires an OCD tool called a spectroscopic ellipsometer. This tool is used in conjunction with a measurement technique called scatterometry. A transmission electron microscope (TEM) generates reference data for the process.

An ellipsometer is a tool that measures the thickness of thin films. A spectroscopic ellipsometer is an ellipsometer with a broadband light source. Both systems perform what is called ellipsometry, which is a non-destructive, model-based technique. Ellipsometry doesn’t measure the actual device. It measures a structure that mimics the device.

For this, a sample structure is inserted in the ellipsometer and the light hits the target. “With optical scatterometry, we do 3D device-shaped metrology. We are looking at fin shape, gate height and silicon depths. The key is to measure the three-dimensional shapes of the critical devices,” said Raphael Getin, product marketing manager at KLA.

“Spectroscopic ellipsometry is an optical technique used to investigate film thickness, CD and feature shapes. Spectroscopic refers to the fact that data is collected across a range of wavelengths, from deep ultraviolet (DUV) to IR,” Getin explained. “With ellipsometry, you are looking at the phase change of the light. You illuminate a target with polarized light. ‘S’ polarized light is perpendicular to the plane of incidence, and ‘P’ polarized light is parallel to the plane of incidence. The metrology system is looking to see how the signal reflected from the target changes the polarization of the light.”

This system uses a technique called scatterometry, which leverages model libraries to determine the dimensional parameters of structures. “Broadband light, covering wavelengths from DUV to IR, illuminates a target or repeating device structure,” Getin said. “A variety of different measurements can be taken from different illumination angles, to different target orientations, to different illumination or collection polarizations. The reflected light is collected and fed into advanced algorithms that compares the signals to a library of models, created based on known material properties, film thicknesses and other data. The data output shows what is happening with the pattern CD and 3D structures, highlighting small variations that could affect device performance.”

That’s just for the fins of finFETs. In the subsequent process steps for finFETs, chipmakers also want to characterize the composition of the materials, dopants and other parts of the device.

Those steps require the same or different metrology tools. This helps explain why chipmakers require more than a dozen metrology tools to characterize finFETs.

“In general, as the process becomes more complex, the more you need to use these kind of tools,” said Subodh Kulkarni, president and CEO at CyberOptics, in a recent interview.

GAA metrology steps
Today, two foundry vendors — Samsung and TSMC — will extend the finFET to the 5nm node. But finFETs will run out of steam when the fin width reaches 5nm.

So at 3nm, Samsung will migrate to a gate-all-around technology called nanosheet FETs in 2021/2022. TSMC plans to extend the finFET to 3nm, and will introduce gate-all-around later.

Nanosheets provide some price/performance benefits over finFETs, but there is only an incremental reduction in scaling. “The move from finFET to nanosheet is redefining the new era of how an increase in computer power and higher transistor densities will be achieved. It will be about changing the transistor architecture rather than making things smaller,” said Douglas Guerrero, senior technologist at Brewer Science.

A nanosheet FET is a finFET on its side with a gate wrapped around it. A nanosheet consists of several separate and thin horizontal pieces or sheets, which are vertically stacked. Each sheet makes up a channel.

A gate surrounds each sheet, creating a gate-all-around transistor. Nanosheets provide more performance with less leakage because control of the current is accomplished on four sides of the structure.

In the production of nanosheets, chipmakers will deploy many of the existing tools used for finFETs at 7nm/5nm, such as extreme ultraviolet (EUV) lithography. “While the critical dimensions of gate-all-around are similar to finFET, there are several steps in the transistor formation that add additional process and measurement complexity,” KLA’s Getin said.

The nanosheet process starts with the formation of a super-lattice structure on a substrate. An epitaxial tool deposits alternating layers of silicon-germanium (SiGe) and silicon on the substrate. A stack consists of three layers of SiGe and three layers of silicon.

The nanosheet width ranges from 12nm to 16nm with a 5nm thickness. Each layer must be exact. It’s critical to obtain accurate measurements and discern between the silicon and SiGe.

For this, chipmakers likely will use ellipsometry and/or X-ray metrology. “It’s a relatively straightforward measurement for an ellipsometer even though there are thin layers here. Sub-10nm film stacks are standard for ellipsometry,” said Nick Keller, principal technologist at Onto Innovation. “You can measure the repeating layers, and you can even measure the germanium percentage in the SiGe layers with a good model that can track the movement of the critical points in the band structure that red shift with greater germanium incorporation.”

In addition, two X-ray metrology types —X-ray reflectivity (XRR) and high-resolution X-ray diffraction (HRXRD) — are used. XRR handles thin-film measurements, while HRXRD characterizes single-crystal thin-film materials.

“There is a complex epi structure, which is ideally suited to X-ray metrology,” said Paul Ryan, director of product management at Bruker. “Due to the complexity of the structure, with many similar but not identical layers, a traditional approach using just a single measurement does not give the accuracy and precision required. However, by performing a combination of XRR and HRXRD, the individual layer thicknesses and SiGe compositions can be extracted.”

Then, in the nanosheet flow, the next step is to create fins in the super-lattice structure. For this, fins are patterned and etched.

This requires precise CDs with good control. For this, chipmakers will likely use OCD with scatterometry. It may require more measurements.

“The etching and stressor deposition can cause release of stress in the fin, and this can be characterized using HRXRD reciprocal space mapping,” Ryan said. “This is an R&D measurement.”

More and harder steps
Then comes one of the harder steps in nanosheets—the formation of the inner spacers. For this, the outer portions of SiGe layers in the super-lattice structure are slightly recessed using a lateral selective etch process, sometimes called a cavity etch.

This creates inter-spacers in the SiGe layers. Eventually, the spacers are filled with dielectric materials, which reduces the gate to source/drain parasitic capacitance.

The lateral etch process requires precise control without damaging the other parts of the structure. It also requires accurate measurements of the spacers in the SiGe layers. “If the spacers and inter spacers are recessed the same way for GAA as in finFETs, optical metrology will work well for the measurements,” KLA’s Getin said. “If these features are not etched the same way, then current optical metrology solutions may not be adequate. The industry will need to look at metrology solutions that utilize different illumination sources, additional measurement techniques, and/or advanced AI algorithms.”

In one possible solution, Onto, SUNY, and TEL recently presented a paper on a non-destructive approach to characterize a nanowire test structure in the cavity etch process. Vendors used a technique called Mueller matrix spectroscopic ellipsometry (MMSE) based scatterometry.

A spectroscopic ellipsometer provides two parameters. In contrast, MMSE provides 16 pieces of information to the user. “In traditional ellipsometry, you only measure the reflection of the parallel polarized component of the reflected light back into the parallel. And you also measure the amount of perpendicular part of the incident light that is reflected and observed as perpendicularly polarized light. There is cross-polarized light scattering that occurs for many samples, especially many typically used 3D structures,” SUNY’s Diebold explained. “With Mueller matrix capability, you not only get that cross polarized light scattering, but you can include the influence of the imperfections in grating that you’re looking at. For example, it can have sidewall roughness or imperfect patterning. It could also have defects in it. All of that is picked up when you use the Mueller matrix approach.”

MMSE works and is fast, but there are some challenges at the most aggressive pitches. So in R&D, the industry is looking at other solutions.

For instance, Onto, NIST, SUNY and TEL presented some results with the same structure and process using an X-ray metrology technology called critical-dimension small-angle X-ray scattering (CD-SAXS). CD-SAXS uses variable-angle transmission scattering from a small beam size to provide the measurements.

“By using CD-SAXS measurements, we have been able to achieve a model of the structure and also differentiate between small differences in the amount of selective etch,” said Madhulika Korde, a graduate student and research assistant at SUNY. “Our data shows that CD-SAXS is very sensitive to the cavity etch process for the nanowire test structures. This is because as the amount of the etch increases, there’s more contrast between the standing silicon nanosheet and the air, which is now in the cavity that results from the etched silicon germanium. Due to this contrast, we are able to model the structure more accurately and extract the cavity etch information.”

CD-SAXS is a slow and expensive process, and so far it is not ready for prime time. That’s why CD-SAXS remains in the lab, not the fab. “CD-SAXS gives you phenomenal profiles. Because it penetrates through the substrate, you can see layers of different materials,” said Dan Hutcheson, CEO of VLSI Research. “It’s a scatterometry-type technology like optical scatterometry, but it’s slow.”

Then, in the nanosheet flow, the source/drain is formed. After that, the SiGe layers in the super-lattice structure are removed using an etch process. What’s left are silicon-based layers or sheets, which make up the channels.

Measuring the nanosheets is difficult. “The big metrology inflection in gate-all-around will be the requirement to characterize nanosheets in the ‘z’ direction, as the weakest of the individual sheets will dictate electrical performance of the whole transistor,” KLA’s Getin said. “Optical CD metrology will work for providing fab engineers with an average of the stacked nanosheets. The challenge comes in providing dimensional information on individual nanosheets, which will require innovations in optical techniques and use of machine learning or AI algorithms.”

The next step is the replacement metal gate (RMG) process. “Similar to the finFET multi-Vt process, the RMG module for nanosheets consists of multiple deposition, diffusion, anneal and strip steps to achieve the desired stack work-function,” said Kavita Shah, senior director of strategic marketing at Nova. “Optical techniques lack sensitivity in this thickness regime, and additional film properties such as roughness can further obfuscate optical metrology results.”

This is where a technology called X-ray photoelectron spectroscopy (XPS) fits in. “XPS is a surface-sensitive quantitative spectroscopic technique that measures the elemental composition of thin films. This technique provides information about the chemical state and electronic state of the elements that exist within a thin film or a complicated stack,” Shah said.

XPS is ideal for this step in the nanosheet flow. “Customers use inline XPS to control performance-critical high-k and work-function metal stacks as part of this integrated process module. Typically, the requirement is to control the thickness and stoichiometry of individual films and various materials with thickness ranges of 2Å-15Å,” Shah said.

Then, in the process flow, high-k/metal-gate materials are deposited in the structure. And finally, the copper interconnects are formed, resulting in a nanosheet.

In gate-all-around, there are other process steps. In most cases, the metrology solutions are ready, although there are some question marks.

Perhaps the biggest question is when will the industry migrate to gate-all-around. It’s still unclear. Based on past events, it could take longer than expected.

Related Stories

5/3nm Wars Begin

Moving To GAA FETs

Reliability Challenges Grow For 5/3nm


Masahiko says:

Enjoyed this article!

CB Chuang says:

Are there other approaches that’s not reflection or diffraction based?

Masahiko says:

Yes, there are some ways, if you accept destructive method. For instance, a combination of FIB and TEM/STEM.

Leave a Reply

(Note: This name will be displayed publicly)