Moving To GAA FETs

Why finFETs are running out of steam, and what happens next.


How do you measure the size of a transistor? Is it the gate length, or the distance between the source and drain contacts?

For planar transistors, the two values are approximately the same. The gate, plus a dielectric spacer, fits between the source and drain contacts. The contact pitch, limited by the smallest features that the lithography process can print, determines how many transistors can fit in a given space. For a given process technology, the required silicon area determines the manufacturing cost of the device.

The gate length, on the other hand, helps define the device performance. For most of the industry’s history, shorter gate lengths meant faster devices because the carriers didn’t have to travel as far. Since the end of Dennard scaling, though, performance metrics have become more complicated as devices have behaved less and less like ideal transistors.

Interface scattering reduces carrier mobility in very small devices, while drain-induced barrier lowering (DIBL) and other short channel effects blur the difference between the “on” and “off” states. Overly aggressive gate length scaling makes device performance worse, not better. Manufacturers need to continue to reduce contact pitch to shrink the total silicon area, while reducing the gate length at a more moderate rate. In a recent presentation, TSMC Deputy Director Jin Cai suggested that, based on simulation results, planar transistors are limited to a minimum gate length of about 25nm.

The solution, since 2011 or so, has been to use the third dimension. In a finFET, the channel consists of two or more fins, surrounded on three sides by the gate. Reducing the spacing between fins allows the contact pitch to shrink, while increasing the fin height maintains the desired electrostatics. As the fin width goes down, carrier mobility gets worse due to interface scattering and quantum confinement. Short channel effects improve as the fin width goes down, though, because the gate can control the channel more effectively. For maximum drive current, devices need to balance the two effects. Cai estimated that finFETs can scale to about 2.5X to 3X the fin width.

In work presented at IEDM, Julien Ryckaert and colleagues at Imec estimated that the most compact possible finFET standard cells have 2 fins, 5nm apart, giving an effective gate length of 15 nm. A standard cell contains both an NFET and a PFET transistor, with an optimal spacing between the two to minimize parasitic effects. The minimum spacing between fins is defined by the lithography process, and also by the need to allow space for the gate metal and gate dielectric in between the fins.

As contact pitch continues to shrink, there simply isn’t enough room to fit two or more fins in a standard cell. Eliminating the second fin doesn’t solve the problem either. It’s difficult to increase the fin height enough to compensate for the reduced width. Moreover, Ryckaert explained, having two fins helps compensate for process variability because the combined width of both fins is easier to control than the width of each fin individually.

FinFETs have other disadvantages, too. It’s not possible to make fractional fins, so designers can only specify device dimensions in multiples of whole fins. Fin quantization limits the available options for balancing drive current, leakage, and device performance. Ideally, wider devices are preferred for high performance computing, while narrow devices are used for low-power circuit elements. Being able to choose a wider range of device dimensions would make it easier to accommodate both on the same piece of silicon.

Fig. 1: FinFET vs. nanosheet. Source: Imec

After finFETs, wrap the gate around
For all of these reasons, gate-all-around transistors are emerging as the successors to finFETs for extremely scaled process nodes. GAA devices were first proposed in 1990, Cai said, well before finFETs, but finFETs turned out to be easier to implement in production.

GAA transistors can be based on either nanowires or stacked nanosheets, aligned either parallel or perpendicular to the substrate. Since 2017, according to Huiming Bu, director of advanced logic and memory technology at IBM’s AI Hardware Center, the industry consensus has gradually converged on horizontally stacked nanosheets as the best alternative for the 5nm generation. These devices start with alternating layers of silicon and SiGe, patterned into pillars.

Creating the initial Si/SiGe heterostructure is straightforward, and pillar patterning is similar to fin fabrication. The next several steps are unique to nanosheet transistors, though. An indentation in the SiGe layers makes room for an inner spacer between the source/drain, which will eventually be deposited next to the pillar and the space where the gate will be. This spacer defines the gate width. Then, once the inner spacers are in place, a channel release etch removes the SiGe. ALD deposits the gate dielectric and metal into the spaces between the silicon nanosheets.

To minimize lattice distortion and other defects, the germanium content of the SiGe layers should be as low as possible. Etch selectivity increases with Ge content, though, and erosion of the silicon layers during either the inner spacer indentation or the channel release etch will affect channel thickness and therefore threshold voltage. In work presented at IEDM, Nicolas Loubet and colleagues at IBM Research and TEL Technology Center explained that the conventional vapor phase HCl etch process produces a half-moon meniscus shape along the etch front. Instead, the IBM group demonstrated 150:1 selectivity for Si0.75Ge0.25 relative to silicon, with a rectangular etch front. The improved dimensional control gave better device yield and improved variability for both NFET and PFET transistors.

In finFET transistors, designers use the thickness and composition of the gate metal to adjust its work function and tune the transistor’s threshold voltage. Ideally, according to IBM senior engineer Ruqiang Bao and his colleagues, an attractive logic technology should be able to accommodate at least three different threshold voltage NFET/PFET pairs — six different gates — on the same chip. Nanosheet devices, however, must deposit the gate metal uniformly and conformally into the gaps between nanosheets. After the sacrificial SiGe etch opens these spaces, a mask material of some kind must protect each group of devices in turn while the other gate metals are being deposited. Bao and colleagues proposed the use of a sacrificial material to pinch off the gap openings, so that the mask material does not need to first infiltrate and then be removed from the gaps. This group also demonstrated a “volumeless” approach to threshold voltage tuning, using metal dipoles to tune the work function without changing the overall metal thickness.

Highly scaled planar transistors depend on strain engineering for carrier mobility enhancement. Strain engineering in three-dimensional devices is inherently more challenging due to the complex geometry. In nanosheet transistors, the lattice mismatch between silicon and SiGe is certain to introduce strain, but it is not yet clear whether the effects will be positive or negative. Work done at Leti and IBM combined transmission electron microscopy and modeling techniques to estimate compressive strains of between -0.5% and -1% after the channel release etch. While removal of the sacrificial SiGe appeared to allow relaxation of tensile stress in the silicon, the encapsulation of the source and drain imposed compressive stress. The Leti group was able to deliberately compress the PFET channel regions by cladding the silicon with SiGe.

More scaling, more stacking: Fold the standard cell
Beyond stacked nanosheets, Cai suggested that horizontal nanowires can support scaling well below 10 nm gate lengths, as they can tolerate closer wire-to-wire spacing than nanosheets can. Looking ahead even further, researchers at TSMC proposed vertically complementary FETs, putting the NFET below the PFET in a standard cell. Their design depends on junction-less devices, with two complementary nanosheets separated by an oxide layer. Though it looks radical, the authors note that junction-less devices eliminate a number of lithography steps, and the vertical cell achieves almost a 50% footprint reduction.

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skagon says:

Could you please post a link to that “IEDM paper 11.7”?

Katherine Derbyshire says:

Now that IEEE has uploaded the IEDM papers, I’ve updated all of the links. The full 2019 IEDM proceedings can be found here:

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