Reporting and Benchmarking Process For A 2D Semiconductor FET


New research paper titled "How to Report and Benchmark Emerging Field-Effect Transistors" was published from researchers at NIST, Purdue University, UCLA, Theiss Research, Peking University, NYU, Imec, RWTH Aachen, and others. "Emerging low-dimensional nanomaterials have been studied for decades in device applications as field-effect transistors (FETs). However, properly reporting and compar... » read more

Evaluating The Impact Of STI Recess Profile Control On Advanced FinFET Device Performance


In this paper, a 5nm FinFET flow was built using the SEMulator3D virtual fabrication platform. Different STI (shallow trench isolation) recess profiles were investigated using the pattern-dependent etch capabilities of SEMulator3D, including changes in trenching/footing profile, fin height and imbalance fin height. The impact of STI recess profile on device performance was then investigated usi... » read more

Replacement Gate High-k/Metal Gate nMOSFETs Using A Self-Aligned Halo-Compensated Channel Implant


A device design technique for boosting output resistance (Rout) characteristics of long-channel halo-doped nMOSFETs for replacement gate (RMG) high-k/metal gate (HK/MG) devices is proposed based on numerical simulations. We show that the self-aligned halo-compensated channel implant (HCCI) that is carried out after dummy poly gate removal provides compensation for the conventional halo doping. ... » read more

Moving To GAA FETs


How do you measure the size of a transistor? Is it the gate length, or the distance between the source and drain contacts? For planar transistors, the two values are approximately the same. The gate, plus a dielectric spacer, fits between the source and drain contacts. The contact pitch, limited by the smallest features that the lithography process can print, determines how many transistors ... » read more