Quantum Effects At 7/5nm And Beyond

At future nodes there are some unexpected behaviors. What to do about them isn’t always clear.


Quantum effects are becoming more pronounced at the most advanced nodes, causing unusual and sometimes unexpected changes in how electronic devices and signals behave.

Quantum effects typically occur well behind the curtain for most of the chip industry, baked into a set of design rules developed from foundry data that most companies never see. This explains why foundries and manufacturing equipment companies so far are the only ones that have been directly affected, and they have been making adjustments in their processes and products to account for those effects. But as designs shrink to 7/5nm and beyond, quantum effects are emerging as a more widespread and significant problem, and one that ultimately will affect everyone working at those nodes.

“Quantum effects happen in the device as soon as certain device dimensions become very small, due to scaling and its associated requirements,” said Anda Mocuta, director of technology solutions and enablement at Imec. “For example, as a consequence of gate dielectric scaling and that of the increasing electric fields within the device, the carriers in the inversion layer are no longer located at the silicon dioxide-silicon interface, but somewhere below, resulting in an increased effective dielectric thickness. This effect has existed in CMOS technologies for a while now, and it is a quantum effect. Going forward, more quantum effects are expected due to transistor-body dimension reduction, which is required to maintain electrostatics, and to gate-length reduction.”

Quantum effects have been observed, studied and theorized for years, and not just in the semiconductor industry. Quantum tunneling, for example, has been documented for nearly a century in alpha particle decay research. But in the chip world, these quantum effects show up in a variety of strange behaviors that are becoming increasingly problematic.

“Quantum effects have always been there,” said David Fried, vice president of computational products at Coventor, a Lam Research Company. “You can’t really solve the transistor equation without understanding periodic lattice and quantum effects. The question is the extent to which they influence your ability to understand physical and electrical behavior of the devices. If you go back 10 to 15 years, before we had high-k and metal gate, we had polysilicon depletion effects on one side of the gate, and a quantum confinement effect, where the carrier channel doesn’t sit at the interface of the transistor. It sits a little bit further away because of the density of stage function in the channel of the transistor. That little bit further away from the interface is a quantum effect, and at 130/90/65nm it became a measurable delta in the behavior of the inversion capacitance. We went off and studied, learned it, and built it into our predictive device models. Then we did things like high-k metal gate. Metal gate got rid of the poly depletion. We got better field coupling into the channels and started to do things in technology to reduce some of these quantum effects.”

Fig. 1: Metal gate improvement over poly depletion with associated capacitance and drive current improvement. Source: Intel/MIT

At 7/5nm and beyond, there is a whole new set of worries to add to the list that are associated with quantum effects.

“You can see increased line edge roughness, variability, the potential for opens and shorts where you didn’t expect them,” said Gary Patton, CTO at GlobalFoundries. “It means you have to optimize the ground rules to maximize throughput out of the EUV tool.”

Memory issues and directions
Flash memory was one of the first places that chipmakers began experiencing quantum effects firsthand. Beginning several years ago, NAND memory companies reported seeing unexpected irregularities in how data moved in and out of memory.

“This is one of the main reasons why flash memory moved to vertical NAND,” said G. Dan Hutcheson, CEO of VLSI Research. “The problem is that you don’t necessarily get what you want to get. Systems were designed to work in a stochastic world. But when you move into the quantum world, what should work doesn’t. And there aren’t enough electrons to measure what’s going wrong.”

There is research underway to minimize tunneling by electrons through thin materials. One such approach is a spin lattice, which can localize or “contain” the stray electrons. Spin transfer torque (STT) MRAM changes the spin of electrons using electrical current rather than magnetism.

“The problem with tunneling for years was that it was too slow and too difficult to implement,” said Hutcheson. “Another problem with quantum effects is how you make material consistent enough so you don’t have these problems. This is where some of the big equipment companies have been focused.”

Fig. 2: Schematic of electron wavefunction showing tunneling through thick vs. thin barrier. Source: nanoScience Instruments

Gate tunneling was a key reason for the introduction of high-dielectric-constant gate materials. Their increased physical thickness for a desired equivalent oxide thickness reduces tunneling. But at advanced nodes, that isn’t possible because gate oxides shrink with the rest of the features.

Observing quantum effects
Stepping into the world of quantum physics, quantum effects are largely a function of the dual nature of electrons, both as particles and as waves. While physicists hvae been working with these concepts for decades, they are well outside the scope of electrical engineering. But the fields begin to overlap at 7/5nm and beyond.

“Some aspects we understand well and can deal with, such as threshold voltage adjustments to account for Vt shifts,” said Imec’s Mocuta. “Most aspects we can model and understand well, and we can design knobs to mitigate partially. Some aspects may remain fundamental in nature.”

The list grows by the node. “There are scattering effects,” said Coventor’s Fried. “There are things like volume inversion. When we start talking about really thin finFET devices or even nanowires, instead of having surface inversion, all of sudden the device is fully depleted. You turn it on and the center of the wire will invert before the edges. These are all very interesting effects, but the theory behind it all is still the same. We understand it, we study it, build it into the device models.”

And while quantum physicists may call this elementary, the practical application of these concepts can be quite complicated.

“If you look back through literature, somebody has been writing about it in some way, shape or form,” Fried said. “There’s a lot of predictive capability in some of these effects. Quantum effects become key when you need to build some model, whether it’s a structural, fabrication or device electrical model, which is where it hits the hardest. These devices are so small, and we’re parking them on the precipice of stability in a lot of different ways. So the effects are linked and challenging. With every technology development, it takes years from the time the first person begins working on 7nm until it moves into high-volume manufacturing. Over the course of those years, you’re running into some effect and you’re asking, ‘What is happening here?’ You start to dig in and you realize it’s this effect and that effect. Over the course of those years, you’re running into these things that are interrelated that you didn’t think were coming or didn’t know they would be there, and then you pull it apart and address it.”

The impact isn’t always obvious. For example, Imec’s Mocuta points to transistor body scaling, which is gradually becoming a requirement for maintaining electrostatic control. Quantum effects show up as thinner fins, which ultimately will force a move to gate-all-around transistor structures using nanowires or nanosheets.

That move isn’t far off. Samsung Foundry unfurled its transistor roadmap this week, which included the introduction of gate-all-around FETs starting at 3nm using nanosheets. Yongjoo Jeon, principal engineer at Samsung Foundry, said initial versions of the PDK will arrive next year, with mass production of GAA FETs beginning in 2021. Those chips are expected to provide about a 20% improvement in power and performance, he said, compared with about a 30% to 40% increase in power and performance in previous technology generations.

“At very small dimensions of the body, the semiconductor band structure gets ‘quantized,’ so instead of a continuous energy spectrum for the carriers, for example, only discrete energy levels are allowed,” Mocuta said.

This quantum confinement has several possible consequences. Among them:

• A transistor threshold voltage change.
• A change in the density of states (DOS), or the number of carriers available for current conduction.
• A change in carrier injection velocity.

The transistor threshold voltage change can be readily corrected with process technology. But changes in the DOS and the carrier injection velocity cause drive current changes in the device, said Mocuta. And that, in turn, can affect the performance of a technology built using these transistors.

“Sometimes these are beneficial, while at other times they are not can be easily corrected for by the process,” she said. “These quantum effects become important in silicon if the transistor body dimension is at or below about 7nm.”

As gate length is gradually reduced to accommodate scaling, the consequences show up in two main places. One is in the transistor OFF state, where carriers can more easily tunnel from the source-drain. That results in an increase in OFF current, and higher power consumption. This typically happens for gate lengths below 10nm. The second occurrence is when the carrier transport becomes increasingly ballistic, which occurs at gate lengths below 20nm, said Mocuta.

“There are very few scattering centers between source and drain (resulting in improved current drive and performance/speed),” she said. “Next nodes will scale the fin widths further below 7nm and gate lengths below 20nm, making quantum confinement and ballistic transport more pronounced.”

Exactly how quantum effects will impact designs below 5nm isn’t at all clear at this point. What is clear is that there are more effects to deal with, and much more engineering will be required throughout the supply chain.

Quantum effects used to be considered more of a novelty than a set of critical design criteria. In the future, that is almost certain to change. Below 7nm, chipmaking will dig much deeper into the intersection of electrical engineering and quantum physics. The big question is whether this ultimately will lead to technology advances that can harness these effects. For example, there is research underway to alter the band gap in semiconductors by utilizing free electrons. That research is still in the early stages.

The other possible outcome is that quantum effects will simply be new and expensive annoyances that need to be managed across more designs. Right now, it’s too early to tell, and so far there are very few people talking about it.

—Mark LaPedus contributed to this report.

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Transistor Options Beyond 3nm
Complicated and expensive technologies are being planned all the way to 2030, but it’s not clear how far the scaling roadmap will really go.


Mdf says:

You could bet that 1nm is the limit within the current Classical model of Transistor. Then it will be time for quantum computers to arise.

Sergejs says:

Guys, while you continue to shrink transistors, clock speeds are still horrible. Maybe it’s time for novel device? Organic transistors?

Andrei says:

Over 10GHz we are going into radio frequencies, cpu pins will start to resonate and communication becomes next to impossible, so no freq updates in the foreseeable future.

Responder 10 says:

10 GHz is well into radio frequencies.

some guy says:

radio frequencies, (frequencies used by a radio device) start in the kilohertz..

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