The Race To Glass Substrates


The chip industry is racing to develop glass for advanced packaging, setting the stage for one of the biggest shifts in chip materials in decades — and one that will introduce a broad new set of challenges that will take years to fully resolve. Glass has been discussed as a replacement material for silicon and organic substrates for more than a decade, primarily in multi-die packages. But ... » read more

The Importance Of Secure Data Sharing


When it comes to data accessibility, the terms “secure” and “share” seem like two diametrically opposed words. Conventional wisdom would suggest that any effort to secure data would involve limiting access to that data, while sharing data would involve opening up access to that data for others to view and use. As it turns out, semiconductor operations need to do both. On the one h... » read more

Using Predictive Maintenance To Boost IC Manufacturing Efficiency


Predicting exactly how and when a process tool is going to fail is a complex task, but it's getting a tad easier with the rollout of smart sensors, standard interfaces, and advanced data analytics. The potential benefits of predictive maintenance are enormous. Higher tool uptime correlates with greater fab efficiency and lower operating costs, so engineers are pursuing multiple routes to boo... » read more

Using Deep Learning ADC For Defect Classification For Automatic Defect Inspection


In traditional semiconductor packaging, manual defect review after automated optical inspection (AOI) is an arduous task for operators and engineers, involving review of both good and bad die. It is hard to avoid human errors when reviewing millions of defect images every day, and as a result, underkill or overkill of die can occur. Automatic defect classification (ADC) can reduce the number of... » read more

Overlay Optimization In Advanced IC Substrates


Overlay is becoming a significant problem in the manufacturing of semiconductors, especially in the world of advanced packaging substrates — think panels — the larger the area, the greater the potential for distortion due to warpage. Solving this issue requires more accurate models, better communication through feed forward/feed back throughout the flow, and real-time analytics that are bak... » read more

Chip Industry Week In Review


President Biden announced four new Workforce Hubs to support the CHIPS Act and other initiatives, in Upstate New York, Michigan, Milwaukee, and Philadelphia. The White House also provided economic context and progress updates for the President’s workforce strategy. Samsung began mass production of its ninth-gen industry-first V-NAND chip. Along with one-terabit triple-level cell design, th... » read more

Progress In Wafer And Package Level Defect Inspection


The technology to enable sampling and the need for more metrology and inspection data in a production setting have aligned just in time to address the semiconductor industry’s newest and most complex manufacturing processes. In both wafer and assembly manufacturing, engineering teams have long relied on imaging tools to measure critical features and to inspect for defects after specific pr... » read more

New Strategies For Interpreting Data Variability


Every measurement counts at the nanoscopic scale of modern semiconductor processes, but with each new process node the number of measurements and the need for accuracy escalate dramatically. Petabytes of new data are being generated and used in every aspect of the manufacturing process for informed decision-making, process optimization, and the continuous pursuit of quality and yield. Most f... » read more

Using Automatic Defect Classification To Reduce The Escape Rate Of Defects


Automated optical inspection (AOI) is a cornerstone in semiconductor manufacturing, assembly and testing facilities, and as such, it plays a crucial role in yield management and process control. Traditionally, AOI generates millions of defect images, all of which are manually reviewed by operators. This process is not only time-consuming but error prone due to human involvement and fatigue, whi... » read more

Non-Destructive Metrology Techniques For Measuring Hole Profile In DRAM Storage Node


DRAM storage node profile measurement during high aspect ratio (HAR) etch has been one of the most challenging metrology steps. DRAM storage node profile affects refresh time and device electric quality. So, controlling this profile is one of the key challenges. Conventional 3D modeling in Optical Critical Dimension (OCD) metrology has typically used multiple cylinder stacks. This method cannot... » read more

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