Wafer Probe Struggles To Adapt To Multi-Die Assemblies


Wafer probe, one of the key processes for ensuring reliability in semiconductor manufacturing, is becoming increasingly unreliable in multi-die assemblies and at leading-edge nodes. For much of the semiconductor industry’s history, wafer probe occupied a stable, largely uncontested role in manufacturing. It was understood as a screening step, an electrical checkpoint to identify failing de... » read more

A Clear Advantage: Precision Glass Carrier Inspection For AI And HPC Markets


If you’ve been following the evolution of advanced packaging, you know that the industry is pushing boundaries like never before. From high-performance computing to industry-upending AI devices, the demand for smaller, faster, and more powerful chips is driving innovation at every level. One of the unsung heroes in this transformation: Glass carriers. These carriers are becoming essential ... » read more

Early Zone Correction for Enhanced Overlay Precision in Next-Generation FOPLP Lithography


AI chiplet architectures are driving advanced IC substrates (AICS) toward larger panels, finer line/space, and much tighter overlay budgets. This study presents a lithography strategy that combines ultra-large exposure field and fine-resolution imaging with algorithmic early zone correction (EZC) to reduce alignment-solution errors, the largest item in the lithography overlay budget. In this st... » read more

Secure Data Sharing Becoming Critical For Chip Manufacturing


Semiconductor companies increasingly need to share data to solve problems faster, boost yield, and trace the root cause of failed devices. But to make that work, companies need assurances that their data will be secure, free from data leaks that could result in the loss of valuable IP. Data sharing is becoming critical at leading device nodes, where process variability is starting to consume... » read more

Chip Industry’s Top Videos 2025


Rising complexity, new architectures, and AI's permeation of nearly everything left engineers struggling to keep up in 2025, as evidenced by this year's viewership numbers. Among the hottest topics were verification, agentic AI, DRAM/HBM, optimization of data movement, chiplets, and heterogeneous integration, but there was steady traffic growth across all sectors. Top 10 most-watched videos ... » read more

Smaller Geometries, Bigger Demands: The Role Of OCD In GAA Logic And Vertical Gate DRAM Process Control


AI workloads are pushing the boundaries of compute, memory, and interconnect architectures, and to meet these goals, manufacturers are rapidly accelerating advanced logic and DRAM development. Chief among these innovations: gate-all-around (GAA) logic transistor and vertical gate (VG) DRAM, two device architectures that promise higher performance, improved power efficiency, and greater scalabil... » read more

Metrology Digs Deep To Produce Next-Generation 3D NAND


Each generation of 3D NAND packs about 30% more bits than the previous version, with current devices storing up to 2 terabits of data in a die the size of a fingernail. With new product introductions shrinking from 18 months to every 12 months, chipmakers are constantly innovating to enable this prodigious scaling pace. 3D NAND technology is a core ingredient in mobile phones, solid-state dr... » read more

Enhancing CMP Process Control with Intelligent Line Monitoring & Integrated Metrology


New logic transistor designs, 3D NAND stacking, and DRAM integration introduce more CMP layers and tighter process windows. Traditional metrology approaches struggle to keep pace, especially with the need for high sampling rates, multiple control zones, and improved signal-to-noise ratios. Onto Innovation’s Intelligent Line Monitoring & Control with Integrated Metrology offers a new appro... » read more

Chip Industry Week In Review


China's Hefei Lumiverse Technology reportedly has developed a desktop-sized High Harmonic Generation light source that generates wavelengths as small as 1nm. One customer already has used it to produce 14nm chips, which was the original target node for EUV, according to one report. As a point of comparison, TSMC and Samsung didn't start using EUV until the 7nm node, relying instead on immersion... » read more

Through The Glass: Why The Rapid Development Of TGV Demands Rigorous Analysis


The drive for increased performance is enticing some advanced packaging manufacturers to transition from traditional organic substrates to glass core substrates, a switch that comes with numerous benefits. Compared to organic substrates, glass core offers superior mechanical strength, is better suited for large package sizes, provides improved electrical properties, and has the ability to meet ... » read more

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