tag: Onto Innovation

Tool And Methodology Changes Coming In Fab And Package Automation
By Gregory Haley - 04 Mar, 2026 - Comments: 0

Experts at the table: Semiconductor Engineering sat down to discuss what's changing in semiconductor fabs and packaging houses with Michael Lowman, senior product marketing manager for Data Analytics at Cohu; Aftkhar Aslam, CEO at yieldWerx, Woo Young Han, product marketing director at Onto Innovation; and Lihong Cao, senior director of engineering and technical marketing for ASE. What foll... » read more

Back-End Automation Tackles Growing Complexity
By Gregory Haley - 25 Feb, 2026 - Comments: 0

Experts at the table: Semiconductor Engineering sat down to discuss back-end automation challenges in advanced packaging with Michael Lowman, senior product marketing manager for Data Analytics at Cohu; Aftkhar Aslam, CEO at yieldWerx, Woo Young Han, product marketing director at Onto Innovation; and Lihong Cao, senior director of engineering and technical marketing for ASE. What follows are ex... » read more

When Cleaning Chips Isn’t Clean Enough
By Gregory Haley - 19 Feb, 2026 - Comments: 0

Key Takeaways Contamination is becoming much more difficult to identify at the most advanced nodes, forcing fabs to rethink how control is achieved. Issues may show up as electrical or statistical anomalies, not particles, and not at time zero. Reliable classification is needed to identify critical contamination and reduce time and effort spent on nuisance failures. For much... » read more

Catching Critical Defects In TSVs And Stacked Chips
By Laura Peters - 10 Feb, 2026 - Comments: 0

Key Takeaways Variation is becoming a bigger problem in multi-die assemblies with TSVs and hybrid bonding. Multi-modal approaches are required to test these devices. AI plays a role in improving defect capture rate and distinguishing between yield-killing and false positives. New methods for interconnecting devices using through-silicon vias (TSVs) and hybrid bonding in stac... » read more

Resistance In Advanced Packages Is Now A System-Level Problem
By Gregory Haley - 10 Feb, 2026 - Comments: 0

Key Takeaways Kelvin measurement, which has been in use for decades, is no longer sufficient for addressing resistance in complex chips. The problem is that resistance is no longer concentrated in transistors, and where it does show up isn't always consistent or obvious. Traditional pass/fail approaches need to be replaced by more granular and flexible analytics and methodologies. ... » read more

Chiplets Add More Inspection And Test Steps
By Anne Meixner - 10 Feb, 2026 - Comments: 0

Key Takeaways Ensuring the reliability of multi-die assemblies requires a variety of approaches to detect subsurface defects. Bonds and interconnects are especially problematic and require more inspection insertions. Ensuring reliability requires connecting fragmented data that is often siloed. The shift to multi-die assemblies is forcing changes in how chips are tested and ... » read more

Picosecond Ultrasonics: An Advanced Technology Utilized for Process Control of SiCr Thin Film Resistors
By Onto Innovation - 10 Feb, 2026 - Comments: 0

The bipolar-CMOS-DMOS (BCD) process is an advanced semiconductor technology integrating bipolar, CMOS, and DMOS devices onto a single chip, providing a compact, high-performance platform for the integration of analog, digital, and power circuitry. Thin-film resistors are employed to ensure precise resistance values and minimal temperature coefficients (TCR), thereby delivering enhanced accuracy... » read more

Wafer Probe Struggles To Adapt To Multi-Die Assemblies
By Gregory Haley - 13 Jan, 2026 - Comments: 1

Wafer probe, one of the key processes for ensuring reliability in semiconductor manufacturing, is becoming increasingly unreliable in multi-die assemblies and at leading-edge nodes. For much of the semiconductor industry’s history, wafer probe occupied a stable, largely uncontested role in manufacturing. It was understood as a screening step, an electrical checkpoint to identify failing de... » read more

A Clear Advantage: Precision Glass Carrier Inspection For AI And HPC Markets
By Jason Lin - 13 Jan, 2026 - Comments: 0

If you’ve been following the evolution of advanced packaging, you know that the industry is pushing boundaries like never before. From high-performance computing to industry-upending AI devices, the demand for smaller, faster, and more powerful chips is driving innovation at every level. One of the unsung heroes in this transformation: Glass carriers. These carriers are becoming essential ... » read more

Early Zone Correction for Enhanced Overlay Precision in Next-Generation FOPLP Lithography
By Onto Innovation - 13 Jan, 2026 - Comments: 0

AI chiplet architectures are driving advanced IC substrates (AICS) toward larger panels, finer line/space, and much tighter overlay budgets. This study presents a lithography strategy that combines ultra-large exposure field and fine-resolution imaging with algorithmic early zone correction (EZC) to reduce alignment-solution errors, the largest item in the lithography overlay budget. In this st... » read more

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