How Metrology Tools Stack Up In 3D NAND Devices


Multiple innovations in semiconductor processing are needed to enable 3D NAND bit density increases of about 30% per year at ever-decreasing cost per bit, all of which will be required to meet the nonvolatile storage needs of the big data era. 3D NAND is the first truly three-dimensional device in production. It is both a technology driver for new metrology methods and a significant part of ... » read more

Addressing Yield Challenges In Advanced IC Substrate (AICS) Packaging


No matter how you get your news, it seems like everyone is talking about AI – and it’s either going to usher in a new era of productivity or lead to the end of humankind itself. Regardless, the AI era is here, and it’s just beginning to have an impact on our lives, our jobs and our future. To meet the rigorous demands of AI – along with high-performance compute, 5G and electric vehic... » read more

Using AI To Improve Metrology Tooling


Virtual metrology is carefully being added into semiconductor manufacturing, where it is showing positive results, but the chip industry is proceeding cautiously. The first use of this technology has been for augmenting existing fab processes, such as advanced process control (APC). Controlling processes and managing yield generally do not require GPU processing and advanced algorithms, so t... » read more

Using Machine Learning To Increase Yield And Lower Packaging Costs


Packaging is becoming more and more challenging and costly. Whether the reason is substrate shortages or the increased complexity of packages themselves, outsourced semiconductor assembly and test (OSAT) houses have to spend more money, more time and more resources on assembly and testing. As such, one of the more important challenges facing OSATs today is managing die that pass testing at the ... » read more

Power Semiconductors: A Deep Dive Into Materials, Manufacturing & Business


Whether you’re the owner of the average smartphone, commuting on trains, or driving around in a Tesla, you use power semiconductor devices every day. In a technology-dependent world, these devices are everywhere, and demand for more types of chips using different materials is growing. In the past, most engineers paid little attention to power semiconductors. They were deemed commodity, off... » read more

Metrology Strategies For 2nm Processes


Metrology and wafer inspection processes are changing to keep up with evolving and new device applications. While fab floors still have plenty of OCD tools, ellipsometers, and CD-SEMs, new systems are taking on the increasingly 3D nature of structures and the new materials they incorporate. For instance, processes like hybrid bonding, 3D NAND flash devices, and nanosheet FETs are pushing the bo... » read more

Test Challenges Mount As Demands For Reliability Increase


An emphasis of improving semiconductor quality is beginning to spread well beyond just data centers and automotive applications, where ICs play a role in mission- and safety-critical applications. But this focus on improved reliability is ratcheting up pressure throughout the test community, from lab to fab and into the field, in products where transistor density continues to grow — and wh... » read more

Addressing Total Overlay Drift In Advanced IC Substrate (AICS) Packaging


For years, many in the semiconductor industry have focused on the march toward advanced nodes. As these nodes have decreased in size, the size of input/output (I/O) bumps on the chip has grown smaller. As these bumps shrink, their ability to mate directly to printed circuit boards (PCB) diminishes, which, in turn, leads to the need for an intermediary substrate. Enter the advanced IC substrate ... » read more

As Chiplets Go Mainstream, Chip Industry Players Collaborate to Overcome New Development Challenges


The semiconductor industry is building a comprehensive chiplet ecosystem to seize on the advantages of the devices over traditional monolithic system-on-chips (SoCs) such as improved performance, lower power consumption, and greater design flexibility. With heterogeneous integration (HI) presenting significant challenges, collaboration to fulfill the potential of chiplets has become even more i... » read more

Bump Reliability is Challenged By Latent Defects


Thermal stress is a well-known problem in advanced packaging, along with the challenges of mechanical stress. Both are exacerbated by heterogenous integration, which often requires mingling materials with incompatible coefficients of thermal expansion (CTE). Effects are already showing up and will likely only get worse as package densities increase beyond 1,000 bumps per chip. “You comb... » read more

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