tag: Open-Silicon

Rebalancing Power, Performance And Area
By Ed Sperling - 15 Dec, 2011 - Comments: 0

By Ed Sperling The tradeoffs between performance, power and area are being fine-tuned to a degree never seen before in the IC business, driven partly by complexity, partly by better tools, and partly by the need to gain a competitive edge in specific applications. Just being able to make these kinds of tradeoffs is a technological feat that marries everything from high-level modeling and sy... » read more

Model-Driven Design: Making Progress
By Ed Sperling - 15 Dec, 2011 - Comments: 0

By Ann Steffora Mutschler Model-driven design is coming into its own, in part because the old way of using models at advanced nodes doesn’t always produce usable chips and in part because of the need for making tradeoffs at the earliest stages of the design process. The concept of developing models for IC design is hardly a new one, and it is being done today on a number of levels rangin... » read more

Experts At The Table: Stacked Die And The Supply Chain
By Ed Sperling - 13 Dec, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss the effects of stacking die on the supply chain with Stephen Pateras, production marketing director for silicon test at Mentor Graphics; Javier DeLaCruz, director of manufacturing technology at eSilicon; Colin Baldwin, director of marketing at Open-Silicon; Charles Woychik, director of marketing and technical analysis ... » read more

Experts At The Table: Stacked Die And The Supply Chain
By Ed Sperling - 05 Dec, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss the effects of stacking die on the supply chain with Stephen Pateras, production marketing director for silicon test at Mentor Graphics; Javier DeLaCruz, director of manufacturing technology at eSilicon; Colin Baldwin, director of marketing at Open-Silicon; Charles Woychik, director of marketing and technical analysis ... » read more

3D DRAM Makers Inch Closer To Production
By Ed Sperling - 01 Dec, 2011 - Comments: 0

By Mark LaPedus For some time, DRAM makers have been developing 3D memory chips, but commercial products still are not due out for some time because of technical and cost issues. But the advent of the 3D DRAM era could be near the turning point, as two memory rivals have separately moved to bring their respective technologies closer to production. In one move, Micron Technology Inc. has di... » read more

Derivative Designs Demand Discipline
By Ed Sperling - 20 Oct, 2011 - Comments: 0

By Ann Steffora Mutschler By and large most designs today are derivatives, meaning they don’t start from a blank slate. And while that gives engineering teams a starting point, it also can make adding new IP blocks or changes to the design problematic, with the potential for increased routing and timing issues along with considerable pain to back-end engineers and delays in chip schedules. ... » read more

20nm IP Portability Appears Virtually Impossible
By Ed Sperling - 22 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler Each node on the deep submicron path has brought new challenges to engineering teams, and 20nm is no different. With EUV (extreme ultraviolet) lithography challenges still being worked out, double patterning (DP) instead will be embraced in the manufacturing process most likely until 10nm. Due to the unique nature of DP, IP portability between foundries will become a ... » read more

Experts At The Table: Retrofitting Older Process Nodes
By Ed Sperling - 16 Sep, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down with Walter Ng, vice president of the IP ecosystem at GlobalFoundries; Vishal Kapoor, vice president of marketing for SoC realization at Cadence; Naveed Sherwani, CEO of Open-Silicon; John Heinlein, vice president of marketing at ARM; and Jeff Lukanc, director of engineering at IDT. What follows are excerpts of that conversation, which was held in... » read more

Experts At The Table: Retrofitting Older Process Nodes
By Ed Sperling - 08 Sep, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down with Walter Ng, vice president of the IP ecosystem at GlobalFoundries; Vishal Kapoor, vice president of marketing for SoC realization at Cadence; Naveed Sherwani, CEO of Open-Silicon; John Heinlein, vice president of marketing at ARM; and Jeff Lukanc, director of engineering at IDT. What follows are excerpts of that conversation, which was held in... » read more

Experts At The Table: Multi-Core And Many-Core
By Ed Sperling - 11 Aug, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down with Naveed Sherwani, CEO of Open-Silicon; Amit Rohatgi, principal mobile architect at MIPS; Grant Martin, chief scientist at Tensilica; Bill Neifert, CTO at Carbon Design Systems; and Kevin McDermott, director of market development for ARM’s System Design Division. What follows are excerpts of that conversation. LPE: How does cloud computing... » read more

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