tag: packaging

Smaller Nodes, Much Bigger Problems
By Ed Sperling - 15 Jul, 2020 - Comments: 3

João Geada, chief technologist at Ansys, sat down with Semiconductor Engineering to talk about device scaling, advanced packaging, increasing complexity and the growing role of AI. What follows are excerpts of that conversation. SE: We've been pushing along Moore's Law for roughly a half-century. What sorts of problems are you seeing now that you didn't see a couple nodes ago? Geada: The... » read more

Manufacturing Bits: June 30
By Mark LaPedus - 30 Jun, 2020 - Comments: 0

1μm pitch wafer bonding At the recent IEEE Electronic Components and Technology Conference (ECTC), Imec presented a paper on a fine-pitch hybrid wafer-to-wafer bonding technology for heterogeneous integration. Imec described a way to enable hybrid bond pitches down to 1μm using a novel Cu/SiCN (copper/silicon-carbon-nitrogen) surface topography. Today, the industry is developing or shi... » read more

Interconnect Challenges Grow, Tools Lag
By Brian Bailey - 15 Jun, 2020 - Comments: 2

Interconnects are becoming much more problematic as devices shrink and the amount of data being moved around a system continues to rise. This limitation has shown up several times in the past, and it's happening again today. But when the interconnect becomes an issue, it cannot be solved in the same way issues are solved for other aspects of a chip. Typically it results in disruption in how ... » read more

Using Calibre For Advanced IC Packaging Verification And Signoff
By Mentor, a Siemens Business - 10 Jun, 2020 - Comments: 0

As high density advanced package designs evolve and become more common, an automated LVS-like flow to detect and highlight package connectivity errors is required. We explain the most common package verification issues and how designers can resolve them using using Xpedition Substrate Integrator and Calibre 3DSTACK to provide a significant advantage over traditional LVS flows for HDAP. To re... » read more

High-Speed SerDes At 7/5nm
By Ed Sperling - 02 Jun, 2020 - Comments: 0

Manmeet Walia, senior product marketing manager at Synopsys, talks with Semiconductor Engineering about how to optimize PHYs for integration on all four corners of an SoC, as well as the PPA implications of moving large amounts of data across and around a chip. » read more

The Need for Speed
By Subodh Kulkarni - 01 Jun, 2020 - Comments: 0

We’ve previously identified the convergence occurring between surface mount technologies (SMT), used to connect packaged semiconductor devices on printed circuit boards, and advanced packaging (AP) technologies, in which connections between the semiconductor devices and to the outside world are incorporated in the packaging process using front-end-like, wafer-or panel-based manufacturing proc... » read more

Packaging And Package Design For AI At The Edge
By Andy Heinig - 12 Mar, 2020 - Comments: 0

Industrial applications will acquire significantly more data directly from machines in coming years. To properly handle this increase in data, it must already be prepared at the machine. The data of the individual sensors can be processed, or an initial data merger can take place here at the so-called “edge.” Algorithms and methods from the field of artificial intelligence increasingly a... » read more

Demystifying Mirror Types
By Tyler Lockman - 12 Mar, 2020 - Comments: 0

I’m not talking about carnival funhouse mirrors, but rather the different options for mirroring symbols, vias, and bond fingers in your IC Package layout. The Allegro Package Designer Plus and SiP Layout tools have two distinct styles of mirroring which are used in different places. Often, I get questions about what, exactly, those differences are. And even more, why the styles are used for d... » read more

Where Technology Breakthroughs Are Needed
By Mark LaPedus - 23 Dec, 2019 - Comments: 2

After years of delays, extreme ultraviolet (EUV) lithography is finally in production at the 7nm logic node with 5nm in the works. EUV, a next-generation lithography technology, certainly will help chipmakers migrate to the next nodes. But EUV doesn’t solve every problem. Nor does it address all challenges in the semiconductor industry. Not by a long shot. To be sure, the industry needs... » read more

Into The Cold And Darkness
By Ed Sperling - 12 Dec, 2019 - Comments: 1

The need for speed is limitless. There is far more data to process, and there is competition on a global scale to process it fastest and most efficiently. But how to achieve future revs of improvements will begin to look very different from the past. For one thing, the new criteria for that speed are frequently tied to a fixed or shrinking power budget. This is why many benchmarks these days... » read more

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