tag: parallelization

Step Towards A 5G Software-Defined RAN Over A Fully Open-Source Parallel RISC-V Architecture (ETH Zurich)
By Technical Paper Link - 15 Dec, 2022 - Comments: 0

A technical paper titled "Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-core Processor" was published by researchers at ETH Zurich. Abstract (partial) "5G Radio access network disaggregation and softwarization pose challenges in terms of computational performance to the processing units. At the physical layer level, the baseband processing computational effort is typicall... » read more

Research Bits: Oct. 10
By Jesse Allen - 10 Oct, 2022 - Comments: 0

Disposable water-activated battery Researchers at Empa developed a water-activated disposable paper battery that could be used in low-power, single-use disposable electronics such as smart labels for tracking objects, environmental sensors, and medical diagnostic devices. The battery is made of at least one cell measuring one centimeter squared and consisting of three inks printed onto a re... » read more

Dynamically Reconfiguring Logic
By Ed Sperling - 12 Jul, 2021 - Comments: 0

Dynamic reconfiguration of semiconductor logic has been possible for years, but it never caught on commercially. Cheng Wang, co-founder and senior vice president of software and engineering at Flex Logix, explains why this capability has been so difficult to utilize, what’s changed, how a soft logic layer can be used to control when to read, compute, steer, and write data back to memory, and ... » read more

Why It’s So Hard To Create New Processors
By Brian Bailey - 26 Mar, 2020 - Comments: 1

The introduction, and initial success, of the RISC-V processor ISA has reignited interest in the design of custom processors, but the industry is now grappling with how to verify them. The expertise and tools that were once in the market have been consolidated into the hands of the few companies that have been shipping processor chips or IP cores over the past 20 years. Verification of a pro... » read more

Do Parallel Tools Make Sense?
By Brian Bailey - 10 Aug, 2018 - Comments: 0

Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

Your Job is Harder Than Mine
By Ann Mutschler - 11 Oct, 2012 - Comments: 0

What I do for a living is listen – a lot – and try to make sense of the myriad challenges that I hear about in terms of design and managing power and performance. What you do as an architect, design engineer or verification engineer is live in the trenches with it all, every day. I admire and respect that. This is especially true as I recently pondered and talked with industry luminaries... » read more

Keeping The Balance
By Ed Sperling - 13 Sep, 2012 - Comments: 0

By Ann Steffora Mutschler The brains of datacenters today are more powerful than ever due to technology advancements in chip architectures and in manufacturing processes that allow more processing power thanks to Moore’s Law. But knowing exactly how and where to configure the processors and cores for optimum throughput and performance within a certain power budget raises a number of qu... » read more

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