PCIe 5.0 Drill-Down

By Ed Sperling - 01 Apr, 2020 - Comments: 0

Suresh Andani, senior director of product marketing for SerDes IP at Rambus, digs into the new PCI Express standard, why it’s so important for data centers, how it compares with previous versions of the standard, and how it will fit into existing and non-von Neumann architectures. » read more

PCI Express 5 vs. 4: What’s New?

By Rambus - 12 Feb, 2020 - Comments: 0

What’s new about PCI Express 5 (PCIe 5)? The latest PCI Express standard, PCIe 5, represents a doubling of speed over the PCIe 4.0 specifications. We’re talking about 32 Gigatransfers per second (GT/s) vs. 16GT/s, with an aggregate x16 link bandwidth of almost 128 Gigabytes per second (GBps). This speed boost is needed to support a new generation of artificial intelligence (AI) and ma... » read more

Optimizing The Data Center With PCI Express 4.0

By Niraj Mathur - 14 Dec, 2017 - Comments: 1

PCI Express (Peripheral Component Interconnect Express), also known as PCIe, is a high-speed serial computer expansion bus standard designed to replace older PCI, PCI-X and AGP bus standards. Officially launched in 2003, PCIe was rapidly adopted by chip, system and software designers and emerged as the dominant interface standard for connecting peripherals to the CPU. Modern CPUs rely on the... » read more

The Week In Review: IoT

By Jeff Dorsch - 25 Aug, 2017 - Comments: 0

Deals Advanced Semiconductor Engineering was selected by zGlue as its strategic manufacturing partner. The ASE Group will make the zGlue Integrated Platform, which is said to enable customization for consumer and industrial IoT markets. The ZiP integrates hardware and software in a modular 3DIC-based platform. ASE will assemble zGlue-certified chiplets for connecting through zGlue Smart Fabric... » read more

Three Power-Saving Techniques Using PCI Express IP

By Synopsys - 09 Nov, 2016 - Comments: 0

The increasing data traffic between devices in a computing application environment is causing a large power footprint, and for that reason designers are looking for ways to lower the power consumption of their SoCs during sparse or idle times. The smaller, battery-powered devices are often idle and in deep sleep modes, but these deep power saving modes come at the cost of slow resume times to s... » read more

Meeting Reliability For Automotive Applications With PCI Express

By Richard Solomon - 14 Sep, 2016 - Comments: 0

Automotive electronics such as powertrain and braking controls, Advanced Driver Assistance Systems (ADAS), and other vehicle operations platforms, where reliability is of utmost importance must meet stringent reliability standards. Even an automotive infotainment system is expected to perform flawlessly even under a variety of temperatures, humidity, and vibrations. Reliability is a key compone... » read more

Introduction to the Compute Express Link Standard

By Synopsys - 24 Jul, 2016 - Comments: 0

By Gary Ruggles, Sr. Product Marketing Manager, Synopsys Compute Express Link (CXL), a new open interconnect standard, targets intensive workloads for CPUs and purpose-built accelerators where efficient, coherent memory access between a Host and Device is required. A consortium to enable this new standard was recently announced simultaneously with the release of the CXL 1.0 specification. Th... » read more

Bridging The IP Divide

By Brian Bailey - 14 Apr, 2016 - Comments: 0

The adoption of an IP-based model has enabled designs to keep filling the available chip area while allowing design time to shrink. But there is a divide between IP providers and IP users. It is an implicit fuzzy contract about how the IP should be used, what capabilities it provides, and the extent of the verification that has been performed. IP vendors have been trying to formalize this as mu... » read more

Securing IoE Gateways

By Ernest Worthman - 06 Jul, 2015 - Comments: 0

When we talk about the [getkc id="260" comment="Internet of Everything"], (IoE) we have come to realize that it will really be made up of a lot of different “things. It will envelope everything from home automation to intelligent vehicles, to wearables, to industrial applications, military, infrastructure. The list is almost endless. And there is a lot of discussion about securing these “th... » read more

IP Integration Challenges Increase

By Ed Sperling - 16 Jun, 2015 - Comments: 0

Semiconductor Engineering sat down with Chris Rowen, CTO of [getentity id="22032" e_name="Cadence"]'s IP group; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and mixed-signal IP at [getentity ... » read more

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tag: PCI Express

PCIe 5.0 Drill-Down

PCI Express 5 vs. 4: What’s New?

Optimizing The Data Center With PCI Express 4.0

The Week In Review: IoT

Three Power-Saving Techniques Using PCI Express IP

Meeting Reliability For Automotive Applications With PCI Express

Introduction to the Compute Express Link Standard

Bridging The IP Divide

Securing IoE Gateways

IP Integration Challenges Increase

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