Come Together Right Now Over… Virtual Prototypes

By Malte Doerper - 29 Jun, 2017 - Comments: 0

As a frequent traveler and gadgets enthusiast I love the concept of all my devices being connected. However, more often than not I experience a divide which is sometimes caused by bad software and sometimes caused by missing hardware interfaces. My recent frustration was related to my tablet missing a USB port to upload new maps to my GPS device. The GPS device became a divided, isolated pi... » read more

Building One Interface Subsystem For Multiple IoT SoCs

By Ralph Grundler - 11 May, 2017 - Comments: 0

When designing SoCs for Internet of Things (IoT) applications, designers quickly realize that their most efficient use of resources will result in chips that can address multiple end applications. Consumer products require connectivity or edge devices, and networking or enterprise companies are broadening their reach to home networking and cloud services, like remote processing, that complement... » read more

Cloud Computing Chips Changing

By Ann Mutschler - 19 Apr, 2017 - Comments: 1

An explosion in cloud services is making chip design for the server market more challenging, more diverse, and much more competitive. Unlike datacenter number crunching of the past, the cloud addresses a broad range of applications and data types. So while a server chip architecture may work well for one application, it may not be the optimal choice for another. And the more those tasks beco... » read more

Supporting CPUs Plus FPGAs (Part 3)

By Brian Bailey - 19 Apr, 2017 - Comments: 0

While it has been possible to pair a CPU and FPGA for quite some time, two things have changed recently. First, the industry has reduced the latency of the connection between them and second, we now appear to have the killer app for this combination. Semiconductor Engineering sat down to discuss these changes and the state of the tool chain to support this combination, with Kent Orthner, system... » read more

Conflicting Goals In Data Centers

By Gale Morrison - 06 Apr, 2017 - Comments: 0

Two conflicting goals are emerging inside of data centers—speed at any cost, and the ability to extend hardware well beyond its expected lifetime to amortize that cost. Layered across both of those are concerns about how to move data back and forth more efficiently, how to secure it, and how to best integrate different generations of technology. But these widely different goals have create... » read more

Supporting CPUs Plus FPGAs (Part 1)

By Brian Bailey - 27 Mar, 2017 - Comments: 3

Five Pitfalls In PCIe-Based NVMe Controller Verification

By Saurabh Sharma - 08 Dec, 2016 - Comments: 1

Non-Volatile Memory Express (NVMe) is gaining rapidly in mindshare among consumers and vendors. Some industry analysts are forecasting that PCIe-based NVMe will become the dominant storage interface over the next few years. With its high-performance and low-latency characteristics, and its availability for virtually all platforms, NVMe is a game changer. For the first time, storage devices and ... » read more

An Easier Path To Faster C With FPGAs

By Zibi Zalewski - 22 Nov, 2016 - Comments: 0

For most scientists, what is inside a high-performance computing platform is a mystery. All they usually want to know is that a platform will run an advanced algorithm thrown at it. What happens when a subject matter expert creates a powerful model for an algorithm that in turn automatically generates C code that runs too slowly? FPGA experts have created an answer. More and more, the genera... » read more

Introduction to the Compute Express Link Standard

By Synopsys - 24 Jul, 2016 - Comments: 0

By Gary Ruggles, Sr. Product Marketing Manager, Synopsys Compute Express Link (CXL), a new open interconnect standard, targets intensive workloads for CPUs and purpose-built accelerators where efficient, coherent memory access between a Host and Device is required. A consortium to enable this new standard was recently announced simultaneously with the release of the CXL 1.0 specification. Th... » read more

Can IP Integration Be Automated?

By Ann Mutschler - 24 Sep, 2015 - Comments: 1

What exactly does it mean to automate [getkc id="43" comment="IP"] integration? Ask four people in the industry and you’ll get four different answers. “The key issue is how you can assemble the hardware as quickly as you can out of pre-made pieces of IP,” said Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]. To Simon Rance, senior product manager in the ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: PCIe