tag: PCIe

Next-Gen SerDes Roadmap
By Ed Sperling - 25 May, 2021 - Comments: 0

An explosion in data is causing a series of successive bottlenecks in the data center. Priyank Shukla, product marketing manager for high-speed SerDes IP at Synopsys, digs into the performance roadmap for moving data within server racks and between different racks, where the bottlenecks are today, and how they will be addressed in the future. Related SerDes Knowledge Center Top stories... » read more

PCI Express 5.0 Takes Center Stage For Data Centers
By Vinitha Seevaratnam - 08 Apr, 2021 - Comments: 0

The demands on servers at the heart of data centers continue an inexorable rise. Responding to these demands, new platforms keep coming that deliver greater computing performance, have more memory and use faster interconnects. On the way at the end of this year and early 2022 are new server platforms that will take performance to a new level. These new platforms will transition to DDR5 DIMMs fo... » read more

Safeguarding Data Over PCIe & CXL In Data Centers
By Dana Neustadter - 01 Apr, 2021 - Comments: 0

As more devices enter the market and drive exponential growth of data in the cloud, cloud computing is going through a significant overhaul. The increasing presence of “hyperscale” cloud providers for big data and analytics, 5G for rapid IoT connectivity, and the wide use of AI for natural data processing and for extracting insights are compounding both the amount of connected data and the ... » read more

Re-Architecting SerDes
By Brian Bailey - 10 Dec, 2020 - Comments: 0

Serializer/Deserializer (SerDes) circuits have been helping semiconductors move data around for years, but new process technologies are forcing it to adapt and change in unexpected ways. Traditionally implemented as an analog circuit, SerDes technology has been difficult to scale, while low voltages, variation, and noise are making it more difficult to yield sufficiently. So to remain releva... » read more

Making IC Test Faster And More Accessible: Part 1
By Robert Ruiz - 30 Oct, 2020 - Comments: 0

The fundamental challenges of IC test have been the same for a long time. At the heart of all test strategies is controllability and observability. First, control the state of the chip with known test vectors and then observe the chip to determine if it exhibits good or faulty behavior. There have been many innovations over the years to make the required testing of chips more tractable. Thanks ... » read more

Productivity Keeping Pace With Complexity
By Brian Bailey - 24 Sep, 2020 - Comments: 0

Designs have become larger and more complex and yet design time has shortened, but team sizes remain essentially flat. Does this show that productivity is keeping pace with complexity for everyone? The answer appears to be yes, at least for now, for a multitude of reasons. More design and IP reuse is using more and larger IP blocks and subsystems. In addition, the tools are improving, and mo... » read more

PCIe 5.0: A Key Interface Solution For The Evolving Data Center
By Vinitha Seevaratnam - 10 Sep, 2020 - Comments: 0

A great many developments are shaping the evolution of the data center. Enterprise workloads are increasingly shifting to the cloud, whether these be hosted or colocation implementations. The nature of workload traffic is changing such that data centers are architected to manage greater east-west (within the data center) communication. New workloads, with AI/ML (artificial intelligence/machine ... » read more

Accelerating Simulation Of PCIe Controllers For DMA Applications
By Akshay Sarup - 10 Sep, 2020 - Comments: 0

For memory-intensive and high-performance computing, direct memory access (DMA) is indispensable. A typical DMA operation in PCI Express (PCIe) entails the transfer of data from the system memory to end point devices using a point-to-point PCIe bus to reduce latency and increase memory access throughput between the CPU and the device. Verification of DMA engines is concentrated on the data t... » read more

Astera Labs: Purpose-Built Connectivity
By Ed Sperling - 14 Aug, 2020 - Comments: 0

Growing amounts of data are forcing companies to rethink where data is processed and when, how and where it is moved. But solutions may vary greatly from one company to the next, and from one use case or application to the next. This is forcing the adoption of a heterogenous compute architecture that combines traditional processors, such as CPUs, GPUs and FPGAs, with AI processors and smart net... » read more

How UVM Callbacks Simplify Assertion Validation
By Akshay Sarup - 13 Aug, 2020 - Comments: 0

By Akshay Sarup and Mark Olen Assertions bring immediate benefits to the whole design and verification cycle; thus any challenges engineers face in coding and testing them are worth resolving. When a large number of assertions are to be validated, callbacks save time by eliminating the need to code a new sequence for each scenario. Callbacks also provide more dynamic and fine-grained cont... » read more

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