tag: PCIe

Leveraging Multi-Protocol PHY For PCIe To Cope With SoC Design Complexity
By Cadence - 26 Jan, 2022 - Comments: 0

Now in the post-Moore’s Law era, the fast-evolving semiconductor market is continually geared toward higher performance and feature-rich integrated chip (IC) solutions. More functional design blocks integrated with growing interconnections—to not only increase the overall throughput but also expand the I/O connectivity—resulted in a more powerful system on chip (SoC). This increasing comp... » read more

Advancing Signaling Rates To 64 GT/s With PCI Express 6.0
By Tim Messegee - 13 Jan, 2022 - Comments: 0

From the introduction of PCI Express 3.0 (PCIe 3.0) in 2010 onward, each new generation of the standard has offered double the signaling rate of its predecessor. PCIe 3.0 saw a significant change to the protocol with the move from 8b/10b to highly efficient 128b/130b encoding. The PCIe 6.0 specification, now officially released, doubles the signaling rate to 64 gigatransfers per second (GT/s) a... » read more

Interop Shift Left: Using Pre-Silicon Simulation for Emerging Standards
By Cadence - 22 Nov, 2021 - Comments: 0

The Compute Express Link (CXL) 2.0 specification, released in 2020, accompanies the latest PCI Express (PCIe) 5.0 specification to provide a path to high-bandwidth, cache-coherent, low-latency transport for many high-bandwidth applications such as artificial intelligence, machine learning, and hyperscale applications, with specific use cases in newer memory architectures such as disaggregated a... » read more

1.6 Tb/s Ethernet Challenges
By Ed Sperling - 16 Nov, 2021 - Comments: 0

Moving data at blazing fast speeds sounds good in theory, but it raises a number of design challenges. John Swanson, senior product marketing manager for high-performance computing digital IP at Synopsys, talks about the impact of next-generation Ethernet on switches, the types of data that need to be considered, the causes of data growth, and the size and structure of data centers, both in the... » read more

Has Computational Storage Finally Arrived?
By Andy Patrizio - 11 Aug, 2021 - Comments: 2

The idea behind computational storage is not new. It’s just that like so many concepts, the idea has been well ahead of the technology. In a nutshell, computational storage brings processing power to the storage level. It eliminates the need to load data from the storage system into memory for processing. Moving data between storage and compute resources is inefficient and computational sy... » read more

New Power, Performance Options At The Edge
By Heidi Elliott - 21 Jul, 2021 - Comments: 0

Increasing compute intelligence at the edge is forcing chip architects to rethink how computing gets partitioned and prioritized, and what kinds of processing elements and memory configurations work best for a particular application. Sending raw data to the cloud for processing is both time- and resource-intensive, and it's often unnecessary because most of the data collected by a growing nu... » read more

Retimers Replacing Redrivers As Signal Speeds Increase
By Bryon Moyer - 08 Jul, 2021 - Comments: 1

Retimers are undergoing a renaissance as new PHY protocols prove too demanding for redrivers. Redrivers and retimers both have been used to extend wired signal reach over the years. But redrivers have dominated this space due to their relative simplicity and lower cost. That balance is beginning to change. “A retimer represents three things no one wants in their system — area, cost, a... » read more

CXL Signals A New Era Of Data Center Architecture
By Tim Messegee - 08 Jul, 2021 - Comments: 0

An exponential rise in data volume and traffic across the global internet infrastructure is motivating exploration of new architectures for the data center. Disaggregation and composability would move us beyond the classic architecture of the server as the unit of computing. By separating the functional components of compute, memory, storage and networking into pools, composed on-demand to matc... » read more

Challenges In Developing A New Inferencing Chip
By Ed Sperling - 01 Jul, 2021 - Comments: 0

Cheng Wang, co-founder and senior vice president of software and engineering at Flex Logix, sat down with Semiconductor Engineering to explain the process of bringing an inferencing accelerator chip to market, from bring-up, programming and partitioning to tradeoffs involving speed and customization.   SE: Edge inferencing chips are just starting to come to market. What challenges di... » read more

Getting Ready For An Efficient Shift To PCI Express 6.0 Designs With Optimized IP
By Gary Ruggles - 10 Jun, 2021 - Comments: 0

PCI Express (PCIe) 6.0 technology with key changes will bring about challenges that high-performance computing, artificial intelligence, and storage system-on-chip (SoC) designers will face. This article provides designers a summary of the major changes and how they can be handled to ensure a smooth and successful transition to PCIe 6.0. The three major changes in PCIe 6.0 that designers nee... » read more

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