Challenges For A Post-Moore’s Law World


Semiconductor Engineering sat down to discuss challenges at the edge, the impact of open-source, and how to attract new talent, with Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of IC EDA at Mentor, a Siemens Business; Raik Brinkmann, CEO of OneSpin Solutions; Babak Taheri, CEO of Silvaco; John Kibarian, CEO of PDF Solutions; and Prakash Narain, CEO of Real Intent. The con... » read more

Advanced Packaging Makes Testing More Complex


The limits of monolithic integration, together with advances in chip interconnect and packaging technologies, have spurred the growth of heterogeneous advanced packaging where multiple dies are co-packaged using 2.5D and 3D approaches. But this also raises complex test challenges, which are driving new standards and approaches to advanced-package testing. While many of the showstopper issues... » read more

Monitoring IC Abnormalities Before Failures


The rising complexities of semiconductor processes and design are driving an increasing use of on-chip monitors to support data analytics from an IC’s birth through its end of life — no matter how long that projected lifespan. Engineers have long used on-chip circuitry to assist with manufacturing test, silicon debug and failure analysis. Providing visibility and controllability of inter... » read more

Design And Measurement Requirements For Short Flow Test Arrays To Characterize Emerging Memories


Emerging non-volatile memories are becoming increasingly attractive for embedded and storage-class applications. Among the development challenges of Back-End integrated memory cells are long learning cycle and high wafer cost. We propose a short-flow based characterization of Memory Arrays using a Cross Point Array approach. A detail analysis of design requirements and testability confirms feas... » read more

Data Becomes Key For Next-Gen Chips


Data has become vital to understanding the useful life of a semiconductor — and the knowledge gleaned is key to staying competitive beyond Moore’s Law. What's changed is a growing reliance earlier in the design cycle on multiple sources of data, including some from further right in the design-through-manufacturing flow. While this holistic approach may seem logical enough, the semiconduc... » read more

Chip Reliability Vs. Cost


Semiconductor Engineering sat down to discuss the cost, reliability and security with Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of IC EDA at Mentor, a Siemens Business; Raik Brinkmann, CEO of OneSpin Solutions; Babak Taheri, CEO of Silvaco; John Kibarian, CEO of PDF Solutions; and Prakash Narain, CEO of Real Intent. What follows are excerpts of that virtual conversation... » read more

2020 CEO Outlook


Semiconductor Engineering sat down to discuss the semiconductor industry's outlook and what's changing with Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of IC EDA at Mentor, a Siemens Business; Raik Brinkmann, CEO of OneSpin Solutions; Babak Taheri, CEO of Silvaco; John Kibarian, CEO of PDF Solutions; and Prakash Narain, CEO of Real Intent. The conversation was part of the... » read more

Using ML In Manufacturing


How to prevent early life failures by applying machine learning to different use cases, and how to interpret models for different tradeoffs on reliability. Jeff David, vice president of AI solutions at PDF Solutions, digs down into how to utilize data to improve reliability. » read more

Using Fab Sensors To Reduce Auto Defects


The semiconductor manufacturing ecosystem has begun collaborating on ways to effectively use wafer data to meet the stringent quality and reliability requirements for automotive ICs. Silicon manufacturing companies are now leveraging equipment and inspection monitors to proactively identify impactful defects prior to electrical test. Using machine learning techniques, they combine the monitor ... » read more

IEEE S3S 2019 — Characterization Challenges And Solutions For FDSOI Technologies


FDSOI technology has been proposed as an alternative device scaling path which offers benefits of tunable, superior electrostatics transistor while maintaining simplicity of planar integration. New device type and integration elements brought up challenges in device and process characterization and monitoring across the whole lifecycle of the technology. This paper presents successful applicati... » read more

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