tag: performance

Shift Left Your FPGA Design For Faster Time To Market
By Synopsys - 10 May, 2017 - Comments: 0

In just a few short years, FPGAs have become an integral part of system design for many applications either as a co-processor or the main system processor. As FPGA size and performance increases, system designers are able to utilize them for more tasks. The increased size and performance translates to greater complexity, which is further compounded as designers try to integrate more functionali... » read more

Intelligent Power Allocation
By Arm - 12 Apr, 2017 - Comments: 0

The modern System-on-Chip (SoC) has higher thermal dissipation than its previous generations, because of the following factors: Increasing processor frequencies. Decreasing SoC package and device sizes. Higher levels of integration. Static power consumption trends with the most advanced SoC fabrication[1]. Faster frequencies mean faster switching, which means more power consumption... » read more

Tech Talk: Earlier Software
By Ed Sperling - 02 Nov, 2016 - Comments: 0

Malte Doerper, senior manager of product management at Synopsys, talks about the big "shift left" for software, where the problems crop up, and how to save as much as a year of development time with automation and better methodologies.   Related Stories Bridging Hardware And Software The need for concurrent hardware-software design and verification is increasing, but are engine... » read more

Overcoming The Limits Of Scaling
By Ed Sperling - 27 Oct, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the increasing reliance on architectural choices for improvements in power, performance and area, with [getperson id="11425" comment=" Sundari Mitra"], CEO of [getentity id="22535" comment="NetSpeed Systems"]; Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]; [getperson id="11032" comment="Simon Davidmann"] CEO of [getentit... » read more

The Zen Of Processor Design
By Ed Sperling - 15 Sep, 2016 - Comments: 0

Mark Papermaster, chief technology officer at Advanced Micro Devices, sat down with Semiconductor Engineering to discuss how to keep improving performance per watt, new packaging options, and the increasing focus on customization for specific tasks. What follows are excerpts of that conversation. SE: As we get more into the IoT and we have to deal with more data, not to mention cars where da... » read more

How Do We Get To Full Throttle In Mobile?
By Brian Fuller - 16 Jun, 2016 - Comments: 0

By Govind Wathan and Brian Fuller With each new generation of mobile device, we look forward to running the latest apps—especially games. (It's amazing how immersive mobile games have become in just a few years). We’re consumers but we’re also engineers, and here we’re faced with a huge challenge. It’s not just the games that get more powerful. A whole new generation of virtual ... » read more

No More Straight Lines
By Ed Sperling - 12 May, 2016 - Comments: 0

Shrinking features on a chip is no longer the only way forward, and in an increasing number of designs and markets, it is no longer the best way forward. Power and performance are generally better dealt with using different architectures and microarchitectures, and all of those provide the potential to reduce silicon area (cost). Cramming more transistors on a die and working around leakage... » read more

System-Level Verification Tackles New Role
By Brian Bailey - 28 Apr, 2016 - Comments: 0

Wally Rhines, chairman and CEO of Mentor Graphics, gave the keynote at DVCon this year. He said that if you pull together a bunch of pre-verified IP blocks, it does not change the verification problem at the system level. That sounds like a problem. There are assumptions made that the IP blocks work to a reasonable degree, and that when performing system-level verification the focus is not a... » read more

2.5D Becomes A Reality
By Ed Sperling - 14 Apr, 2016 - Comments: 2

Semiconductor Engineering sat down to discuss 2.5D and advanced packaging with Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; John Shin, vice president at [getentity id="22903" e_name="Marvell"]; Bill Isaacson, director of ASIC marketing at [getentity id="22242" e_name="eSilicon"]; Frank Ferro, senior di... » read more

Optimizing DDR Memory Subsystem Efficiency
By Synopsys - 24 Feb, 2016 - Comments: 0

The memory subsystem sits at the core of a System-on-Chip (SoC) platform and can make all the difference between a well-designed system meeting its performance requirements and a system that delivers poor performance, or even fails to operate correctly. State-of-the-art DDR memory controllers use advanced arbitration and scheduling policies to optimize DDR memory efficiency. At the same time, t... » read more

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