UMI Can Scale the Memory Wall

By Eliyan - 25 Sep, 2024 - Comments: 0

While the improvements in processor performance to enable the incredible compute requirements of applications like Chat-GPT get all the headlines, a not-so-new phenomenon known as the memory wall risks negating those advancements. Indeed, it has been clearly demonstrated that as CPU/GPU performance increases, wait time for memory also increases, preventing full utilization of the processors. ... » read more

UMI Can Scale the Memory Wall

By Eliyan - 25 Sep, 2024 - Comments: 0

Photonics Could Reduce The Cost Of Lidar

By Karen Heyman - 05 Sep, 2024 - Comments: 0

Using light to move data over shorter distances is becoming more common, both because there is much more data to move around and because photons are faster and cooler than electrons. Using optical fiber for mission-critical communication is already well established. It has been the preferred PHY for long-haul communications for decades because it doesn’t suffer from the attenuation losses ... » read more

Chiplets and the Early Adopter’s Dilemma

By Eliyan - 28 Aug, 2024 - Comments: 0

Early adopters of a new technology often face a serious dilemma. On one hand, moving early means exploiting the most aggressive new technology available. But on the other hand, making early technology decisions can lock a product line into a path that will later become uncompetitive—either a single-vendor solution that can’t guarantee continuity of supply, or a roadmap that can’t shift an... » read more

224Gbps PHY For The Next Generation Of High Performance Computing

By Priyank Shukla - 18 Jul, 2024 - Comments: 0

Large language models (LLMs) are experiencing an explosive growth in parameter count. Training these ever-larger models requires multiple accelerators to work together, and the bandwidth between these accelerators directly limits the size of trainable LLMs in High Performance Computing (HPC) environments. The correlation between the LLM size and data rates of interconnect technology herald a... » read more

MIPI Deployment In Ultra-Low-Power Streaming Sensors

By Mixel - 13 Mar, 2024 - Comments: 0

Streams of data from higher-speed sensors pose throughput and latency challenges for designers. However, optimizing a design for those criteria can come at the expense of increased power consumption if not conceived and executed carefully. A device like a high-resolution, high-frame-rate home security camera in a non-wired application requiring frequent battery changes or recharging will likely... » read more

Step Towards A 5G Software-Defined RAN Over A Fully Open-Source Parallel RISC-V Architecture (ETH Zurich)

By Technical Paper Link - 15 Dec, 2022 - Comments: 0

A technical paper titled "Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-core Processor" was published by researchers at ETH Zurich. Abstract (partial) "5G Radio access network disaggregation and softwarization pose challenges in terms of computational performance to the processing units. At the physical layer level, the baseband processing computational effort is typicall... » read more

Jitter Budgeting For Clock Distribution Networks In High-Speed PHYs And SerDes

By Synopsys - 07 Dec, 2022 - Comments: 0

This paper presents a simple but practically precise estimation of periodic single-tone power supply induced jitter (PSIJ) for MOS clock buffer chains. The estimation is algebraically simple for its analytical closed-form expression requiring only a few circuit simulation results without the pre-knowledge of circuit device SPICE parameters. The expression is well suited to predict period PSIJ, ... » read more

GUC GLink Test Chip Uses In-Chip Monitoring And Deep Data Analytics For High Bandwidth Die-To-Die Characterization

By proteanTecs - 11 Oct, 2022 - Comments: 0

Advanced ASIC leader Global Unichip Corp (GUC) has developed GLink, a high-bandwidth, low-latency, and power-efficient die-to-die (D2D) interface. GLink offers the industry’s highest optimized interconnect solution for both CoWoS and InFO packaging technologies. The GUC and proteanTecs collaboration started with GUC’s second generation of GLink, known as GLink 2.0. The project target was... » read more

Co-Packaged Optics And The Evolution Of Switch/Optical Interconnects In Data Centers

By Synopsys - 27 Oct, 2021 - Comments: 0

Driven by a need to reduce power and increase bandwidth density in data center network switches and other devices, the data networking industry is moving toward adoption of co-packaged optics (CPO). This paper provides a brief overview of the history of copper and optical interconnects, the limitations of existing interconnect solutions, and the future of co-packaged optics, including the benef... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: PHY

UMI Can Scale the Memory Wall

UMI Can Scale the Memory Wall

Photonics Could Reduce The Cost Of Lidar

Chiplets and the Early Adopter’s Dilemma

224Gbps PHY For The Next Generation Of High Performance Computing

MIPI Deployment In Ultra-Low-Power Streaming Sensors

Step Towards A 5G Software-Defined RAN Over A Fully Open-Source Parallel RISC-V Architecture (ETH Zurich)

Jitter Budgeting For Clock Distribution Networks In High-Speed PHYs And SerDes

GUC GLink Test Chip Uses In-Chip Monitoring And Deep Data Analytics For High Bandwidth Die-To-Die Characterization

Co-Packaged Optics And The Evolution Of Switch/Optical Interconnects In Data Centers