Leading Chip Maker Rolls Out SoC For Automotive Market With NetSpeed Gemini

By NetSpeed Systems - 26 Jul, 2016 - Comments: 0

There is tremendous growth in the automotive IC market due to the trend towards electric or hybrid cars and applications for enhanced safety. However, the technical challenges of implementing today's connected car and the autonomous vehicles of the future are daunting. To read more, click here. » read more

IC Compiler II Multi-Level Physical Hierarchy Floorplanning

By Synopsys - 27 Jan, 2016 - Comments: 0

Large, complex SoC designs require hierarchical layout methodologies that span multiple levels of physical hierarchy. Many EDA tools only handle two levels of physical hierarchy at a given time resulting in longer layout schedules that are risky at best. Synopsys' IC Compiler II provides automation designs with multiple levels of hierarchy that minimizes time to results, provides best QoR, and ... » read more

Tear Down The Wall Between Front-End And Back-End Teams

By Kurt Shuler - 25 Jun, 2015 - Comments: 1

As complexity of system-on-chip devices increases, it's becoming imperative for design teams and organizations to re-examine how they work with one another in order to improve productivity. One giant step in this direction is to bridge the divide between the front-end design process and the physical back-end design process. We often refer to this as a figurative “wall,” but there is real... » read more

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tag: physical design

Leading Chip Maker Rolls Out SoC For Automotive Market With NetSpeed Gemini

IC Compiler II Multi-Level Physical Hierarchy Floorplanning

Tear Down The Wall Between Front-End And Back-End Teams

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