tag: planar

PLANAR: A Programmable Accelerator For Near-Memory Data Rearrangement
By Arm - 12 Oct, 2022 - Comments: 0

Many applications employ irregular and sparse memory accesses that cannot take advantage of existing cache hierarchies in high performance processors. To solve this problem, Data Layout Transformation (DLT) techniques rearrange sparse data into a dense representation, improving locality and cache utilization. However, prior proposals in this space fail to provide a design that (i) scales with m... » read more

Best Practices For Efficient And Effective Planar EM Simulation
By Cadence - 21 Apr, 2021 - Comments: 0

Designers of today’s complex, multi-featured communications products require accurate and fast electromagnetic (EM) simulation to deliver cost-effective, high-performance products to market in ever-shrinking windows of opportunity. The Cadence AWR AXIEM 3D planar method-of-moments (MoM) EM analysis simulator within the AWR software portfolio delivers the accuracy, capacity, and speed designer... » read more

The Great Imbalance
By Ed Sperling - 23 Jul, 2015 - Comments: 2

The number of options for chipmakers is growing while the number of chipmakers is shrinking. So what does this mean for the semiconductor industry? Short answer: No one is quite sure yet. But a lot more people are beginning to ask that question these days, including investors and analysts. There are a number of factors at play here. To begin with, there are more nodes to choose from than at ... » read more

Time To Look At SOI Again
By Mark LaPedus - 16 Oct, 2014 - Comments: 0

Chipmakers have the luxury of looking at several process options when developing chips at the 28nm node and beyond. Using bulk CMOS, for example, chipmakers can scale planar transistors down to 20nm. Then, at 20nm, planar runs out of gas due to the so-called short-channel effect. At that point, IC makers must migrate towards finFETs at 16nm/14nm and beyond. Another process option is fully... » read more

Leti Outlines FDSOI And Monolithic 3D IC Roadmaps
By Mark LaPedus - 14 Nov, 2013 - Comments: 0

Semiconductor Engineering discussed the future roadmaps for fully depleted silicon-on-insulator (FDSOI) technology and monolithic 3D chips with Maud Vinet, manager for the Innovative Devices Laboratory at CEA-Leti. SE: What are some of the technologies being developed at the Innovative Devices Laboratory? Vinet: The Innovative Devices Laboratory is involved with advanced CMOS. So basically... » read more

FD-SOI bests FinFETs for mobile multimedia SOCs? ST says yes.
By Various Writers - 29 Nov, 2011 - Comments: 0

In a recent and excellent article in ASN by Thomas Skotnicki, Director of the Advanced Devices Program at STMicro, he explains in a very clear and accessible way why FD-SOI with ultra-thin Body & Box (UTBB) is a better solution for mobile, multimedia SOCs than FinFETs -- starting at the 28nm node and running clearly through 8nm.  It is based on the paper he presented at the 2011 IEEE SOI C... » read more

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