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SARA: Scaling a Reconfigurable Dataflow Accelerator


Yaqi Zhang, Nathan Zhang, Tian Zhao, Matt Vilim, Muhammad Shahbaz, Kunle Olukotun (Stanford) Abstract—"The need for speed in modern data-intensive workloads and the rise of “dark silicon” in the semiconductor industry are pushing for larger, faster, and more energy and areaefficient architectures, such as Reconfigurable Dataflow Accelerators (RDAs). Nevertheless, challenges remain in d... » read more

Plasticine: A Reconfigurable Architecture For Parallel Patterns (Stanford)


Source: Stanford University Stanford University has been developing Plasticine, which allows parallel patterns to be reconfigured. "ABSTRACT Reconfigurable architectures have gained popularity in recent years as they allow the design of energy-efficient accelerators. Fine-grain fabrics (e.g. FPGAs) have traditionally suffered from performance and power inefficiencies due to bit-level ... » read more

More Knobs, Fewer Markers


The next big thing in chip design may be really big — the price tag. In the past, when things got smaller, so did the cost per transistor. Now they are getting more expensive to design and manufacture, and the cost per transistor is going up along with the number of transistors per area of die, and in many cases even the size of the die. That's not exactly a winning economic formula, which... » read more