tag: power domains

Complete Reliability Verification For Multiple-Power-Domain Designs
By Siemens EDA - 09 Nov, 2022 - Comments: 0

With increasing design complexity and a heightened focus on reliability at all levels of integrated circuit (IC) design from intellectual property (IP) to full-chip, accurate and full verification coverage of the different reliability concerns within an IC design is essential. Designs containing multiple power domains add more complexity to reliability verification with the need to validate int... » read more

Power Domain Implementation Challenges Escalate
By Ann Mutschler - 20 Jun, 2022 - Comments: 0

The number power domains is rising as chip architects build finer-grained control into chips and systems, adding significantly to the complexity of the overall design effort. Different power domains are an essential ingredient in partitioning of different functions. This approach allows different chips in a package, and different blocks in an SoC, to continue running with just enough power t... » read more

SoC Integration Complexity: Size Doesn’t (Always) Matter
By Kurt Shuler - 01 Apr, 2021 - Comments: 2

It’s common when talking about complexity in systems-on-chip (SoCs) to haul out monster examples: application processors, giant AI chips, and the like. Breaking with that tradition, consider an internet of things (IoT) design, which can still challenge engineers with plenty of complexity in architecture and integration. This complexity springs from two drivers: very low power consumption, eve... » read more

An Integrated Approach To Power Domain And CDC Verification
By Kurt Takara - 11 Mar, 2021 - Comments: 0

Reducing power consumption is essential for both mobile and data center applications. Yet it is a challenge to lower power while minimally impacting performance. The solution has been to partition designs into multiple power domains which allow selectively reducing voltage levels or powering off partitions. Traditional low power verification validates only the functional correctness of power... » read more

Power Management And Integration Of IPs In SoCs: Part 1
By Progyna Khondkar - 09 Apr, 2020 - Comments: 0

IPs – whether in the form of soft or hard macros – are the epicenter of today’s SoC designs. Integration of IP with low power designs and conducting power aware (PA) verification are always complex and cumbersome. Because most of these IPs are self-contained, pre-verified at the block level, and must be preserved in their totality when integrated or verified at the SoC level. Until UPF... » read more

Crossed Wires On Domains
By Brian Bailey - 19 Dec, 2019 - Comments: 1

Clock, power and reset domains can form a tangled web if systems are not architected correctly. Wires that cross these domains often require special treatment and additional analysis. They are all evolving independently, meaning that designers must keep up with the latest methodology guidelines and tool capabilities to ensure problems do not remain hidden until they get exposed in silicon. C... » read more

Writing Reusable UPF For RTL And Gate-Level Low Power Verification
By Durgesh Prasad - 08 Aug, 2019 - Comments: 0

By Durgesh Prasad, Jitesh Bansal and Madhur Bhargava The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, and finally during place and route. A major problem is that the UPF needs to be refined or modified at every stage to keep it compatible ... » read more

Overcoming Low Power Verification Challenges For Mixed-Signal SoC Designs
By Himanshu Bhatt - 11 Oct, 2018 - Comments: 0

With increasing SoC complexity and advanced power-aware architectures, a robust low power verification methodology is important for signing off the design at different stages from RTL through netlist. For mixed-signal SoCs, the challenge is, there is no well-defined low power methodology, nor are the industry’s low power verification tools equipped to handle custom designs. This article propo... » read more

Domain Crossing Nightmares
By Brian Bailey - 27 Sep, 2018 - Comments: 1

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

Power Aware Intent And Structural Verification Of Low-Power Designs
By Progyna Khondkar - 08 Mar, 2018 - Comments: 3

Power aware static verification, more popularly known as PA-Static checks, is performed on designs that adopt certain power dissipation reduction techniques through the power intent or [gettech id="31044" t_name="UPF"]. The term static originates from verification tools and methodologies that applies a set of pre-defined power aware (PA) or multi-voltage (MV) rules based on the power requiremen... » read more

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