tag: power formats

Guidelines For Designing Multi-Voltage ICs
By Arvind Narayanan - 17 Jan, 2013 - Comments: 0

By Arvind Narayanan Multi-voltage designs are increasingly common in ICs for mobile devices, but can be difficult to implement. The design flows for multi-voltage architectures are inherently complex and present many new challenges because many blocks are either operating at different voltages or are shut down intermittently. Multi-threshold CMOS switches enable switching off certain portio... » read more

LP Macros 2
By Luke Lang - 14 Jun, 2012 - Comments: 0

By Luke Lang Last month, I compared the CPF macro model with LP attributes in the Liberty model. The CPF macro model was developed when Liberty had very little LP attributes to support LP designs. Even today, Liberty still lacks LP attributes to describe some of the common power intent in LP designs. One example is an LP IP block with internal power switches and shutoff domains. Because mos... » read more

Experts At The Table: ESL Reality Check
By Ed Sperling - 09 Mar, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss electronic-system-level design with Stephen Bailey, director of emerging technologies for the design verification technology group at Mentor Graphics; Michael McNamara, vice president and general manager of Cadence’s System-Level Division; Ghislain Kaiser, CEO of DOCEA Power, and Shawn McCloud, vice president of marketing at Calypto. Wh... » read more

Experts At The Table: ESL Reality Check
By Ed Sperling - 02 Mar, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss electronic-system-level design with Stephen Bailey, director of emerging technologies for the design verification technology group at Mentor Graphics; Michael McNamara, vice president and general manager of Cadence’s System-Level Division; Ghislain Kaiser, CEO of DOCEA Power, and Shawn McCloud, vice president of marketing at Calypto. Wh... » read more

Experts At The Table: ESL Reality Check
By Ed Sperling - 22 Feb, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss electronic-system-level design with Stephen Bailey, director of emerging technologies for the design verification technology group at Mentor Graphics; Michael McNamara, vice president and general manager of Cadence’s System-Level Division; Ghislain Kaiser, CEO of DOCEA Power, and Shawn McCloud, vice president of marketing at Calypto. Wha... » read more

Power Intent Formats: Power Domain
By Luke Lang - 06 Oct, 2011 - Comments: 0

By Luke Lang Starting this month, I will be writing a series of blogs inspired by “Dueling Power Formats”. The article correctly points out that there are currently three power formats: CPF, UPF 1.0, and IEEE 1801. Some designers will find themselves in a position of having to choose a format. Others will need to work with both formats. Regardless of which position one is in, these LP desi... » read more

Dueling Power Formats
By Ed Sperling - 11 Aug, 2011 - Comments: 0

By Ed Sperling Multiple power formats and increasingly complex SoCs don’t sound like a winning formula. So just how bad have things become? Low-Power Engineering asked Sorin Dobre, senior staff engineer at Qualcomm, for a real-world assessment of the situation. LPE: There are three power formats—CPF, UPF and IEEE 1801. How big a problem is this for Qualcomm? Dobre: Actually we have CPF... » read more

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