tag: power grid

Power Complexity On The Rise
By Ann Mutschler - 14 Nov, 2019 - Comments: 0

New chip architectures and custom applications are adding significant challenges to chip design and verification, and the problems are becoming much more complex as low power is added into the mix. Power always has been a consideration in design, but in the past it typically involved different power domains that were either on, off, or in some level of sleep mode. As hardware architectures s... » read more

Containing Design Complexity With POP IP
By Kelvin Low - 16 Nov, 2018 - Comments: 0

About 25 years ago, Carver Mead, one of the pioneers of VLSI design, told a technical audience then grappling with the complexities of quarter-micron design that he could see an evolutionary path to about 130nm, but after that point, the picture blurred. Flash forward to the present and we’re manufacturing SoCs at 7nm, and the output is truly amazing devices powering applications we and Me... » read more

Energy At The Edge
By Ed Sperling - 17 Jul, 2018 - Comments: 0

Ever since the first mention of the IoT, everyone assumed there would be billions of highly efficient battery-powered devices that drew milliwatts of energy. As it turns out, we are about to head down a rather different path. The enormous amount of data that will be gathered by sensors everywhere cannot possibly be sent to the cloud for processing. The existing infrastructure cannot handle i... » read more

5nm Design Progress
By Ann Mutschler - 17 Jul, 2018 - Comments: 1

Activity surrounding the 5nm manufacturing process node is quickly ramping, creating a better picture of the myriad and increasingly complex design issues that must be overcome. Progress at each new node after 28nm has required an increasingly tight partnership between the foundries, which are developing new processes and rule decks, along with EDA and IP vendors, which are adding tools, met... » read more

Managing Voltage Drop At 10/7nm
By Ann Mutschler - 13 Apr, 2017 - Comments: 0

Power integrity is becoming a bigger problem at 10/7nm because existing tools such as static analysis no longer are sufficient. Power integrity is a function of static and dynamic voltage drop in the power delivery network. And until recently, static analysis did an effective job in measuring the overall robustness of PDN connectivity. As such, it is a proxy for PDN strength. The problem is ... » read more

Confidence In 7nm Designs Requires Multi-Variable, Multi-Scenario Analysis
By Sankar Ramachandran - 09 Feb, 2017 - Comments: 0

As designs move toward 7-nanometer (nm) process nodes, engineering and production cost dramatically increases and the stake in getting the design right the first time becomes significantly higher than ever before. You are faced with the question, “how confident are you in your design analysis coverage?” Tighter noise margin, increasing power density, faster switching current and greater ... » read more

Power Confounds, Challenges
By Ann Mutschler - 14 Jul, 2016 - Comments: 0

I have to admit I’m always surprised to hear that design teams are not using tools to the fullest extent possible, leaving valuable power saving opportunities on the table, until I remember how daunting it is to get it all right without tremendous experience, expertise, and the right tools. I’m also always fascinated to learn about less-obvious effects from power. To this point, Aveek... » read more

Low Power Design Analysis
By Ansys - 09 Dec, 2015 - Comments: 0

This paper presents a methodology for comprehensive power grid verification coverage, including identification of power grid weaknesses early in the design cycle. To read more, click here. » read more

Two Constraints-Based Techniques To Address Power-Related Challenges In SoC Design
By Christine Young - 10 Sep, 2015 - Comments: 0

Power scheduling, power integrity targets, voltage drop—these are just a few of the power-related challenges you’re no doubt managing in your SoC designs. There aren’t any easy answers, but there are some emerging—and promising—techniques. Two such techniques, according to University of Toronto Professor Farid Najm, are constraints generation and constraints-based verification. “... » read more

How To Fix Common Power Problems
By Arvind Narayanan - 13 Aug, 2015 - Comments: 0

As the industry moves to ever more advanced technology nodes, managing power has emerged as a primary challenge in modern SoC design. With smaller nodes, the wires become taller and narrower, which increases the resistivity and leads to more pronounced voltage drop effects. Electro-migration effects are also more severe at advanced nodes, causing serious reliability concerns. Both RTL synthesis... » read more

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