tag: power management

System Models Are Changing
By Ed Sperling - 16 Jun, 2011 - Comments: 0

By Pallab Chatterjee Historically system-level modeling was based on making sure there were no timing crashes on the main data bus. After that it was multi-core conflict resolution, distributed memory routing and, most recently, verifying the correct core actually has access to the correct memory with the data that is relevant being available. All of these areas are now subject to an additi... » read more

Low-Power Solutions At DAC
By Bhanu Kapoor - 16 Jun, 2011 - Comments: 0

By Bhanu Kapoor Power is the main driver of semiconductor process technology related advances recently. One would expect a similar focus in the electronic design automation industry to help designers implement low power designs. However, the latest DAC in San Diego didn’t give the impression that the EDA industry is thinking likewise, perhaps with the exception of verification aspects of low... » read more

Power Management Trumps Battery Technology
By Ed Sperling - 10 Feb, 2011 - Comments: 0

By Ann Steffora Mutschler The lithium-ion battery has the power to ruin someone’s day, especially when it dies and cannot be charged, not to mention occasional thermal runaways that literally cause explosions. For a technology that is about 30 years old, and approaching its limits, it is mind-boggling that the best brains on the planet haven’t come up with a technological superior alternat... » read more

Why So Formal?
By Bhanu Kapoor - 21 May, 2010 - Comments: 0

By Bhanu Kapoor Let’s take a look at the types of power management verification issues that are most suited for formal verification and how formal techniques complement dynamic simulation-based verification in some of the challenging tasks associated with validating SoC power management architectures. There are three main categories of formal tools in use today: Equivalence Checkers, Asse... » read more

Optimizing Physical IP For Applications And Processors
By Ann Mutschler - 13 May, 2010 - Comments: 0

What will the next challenges be for chip designers as the industry moves toward 28nm high-k metal gate manufacturing technology? One thing is for sure, power management may get even more painful without new innovations to handle the characteristics of 28nm. Optimization is definitely the approach that keeps creeping up as I talk with folks in the industry with ARM specifically mentioning ap... » read more

Experts At The Table: Low-Power Management And Verification
By Ed Sperling - 19 Mar, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering moderated a panel featuring Bhanu Kapoor, president of Mimasic; John Goodenough, director of design technology at ARM; and Prapanna Tiwari, corporate applications engineer at Synopsys. What follows are excerpts of their presentations, as well as the question-and-answer exchange that followed. Prapanna Tiwari: Traditional techniques like clock-gating an... » read more

Experts At The Table: Low-Power Management And Verification
By Ed Sperling - 11 Mar, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering moderated a panel featuring Bhanu Kapoor, president of Mimasic; John Goodenough, director of design technology at ARM; and Prapanna Tiwari, CAE manager at Synopsys. What follows are excerpts of their presentations, as well as the question-and-answer exchange that followed. Bhanu Kapoor: There are two types of power you need to consider: Dynamic power, ... » read more

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