tag: power

What’s Powering Artificial Intelligence?
By Arm - 11 Sep, 2019 - Comments: 0

While artificial intelligence (AI) and machine learning (ML) applications soar in popularity, many organizations are questioning where ML workloads should be performed. Should they be done on a central processor (CPU), a graphics processor (GPU), or a neural processor (NPU)? The choice most teams are making today will surprise you. To scale artificial intelligence (AI) and machine learning (... » read more

Ensuring A 5G Design Is Viable
By Ed Sperling - 09 Sep, 2019 - Comments: 0

Ron Squiers, network solutions specialist at Mentor, a Siemens Business, explains what’s different in 5G chips versus 4G, how to construct a front haul and back haul system so it is testable in the network stack. » read more

Taking Energy Into Account
By Ann Mutschler - 28 Aug, 2019 - Comments: 1

Considering power throughout the SoC design flow is common practice. The same cannot be said for energy, although that is beginning to change as chips increasingly incorporate heterogeneous processing elements. Combined with this, AI/ML/DL technologies increasingly allow engineering teams to explore and optimize design data for more targeted and efficient systems. But this approach also requ... » read more

Making Security User Friendly
By Brian Bailey - 22 Aug, 2019 - Comments: 0

Serious tradeoffs between technology accessibility and other optimization factors, such as power and security, can crop up especially in the early days of a new product’s design. A new product appeals to a certain category of users who need it to perform well enough that the technology can move forward. They are willing to overlook rough edges in the product and sometimes even glory in the le... » read more

Using Compression For High-Bandwidth Video
By Ed Sperling - 01 Aug, 2019 - Comments: 0

Malte Doerper, senior manager for product management at Synopsys, explains how to improve bandwidth and reduce latency in video without changing out the existing infrastructure through compression, but unlike previous versions of compression there is no significant loss of quality. This approach reduces power, area and heat, as well. » read more

Power Is Limiting Machine Learning Deployments
By Brian Bailey - 25 Jul, 2019 - Comments: 3

The total amount of power consumed for machine learning tasks is staggering. Until a few years ago we did not have computers powerful enough to run many of the algorithms, but the repurposing of the GPU gave the industry the horsepower that it needed. The problem is that the GPU is not well suited to the task, and most of the power consumed is waste. While machine learning has provided many ... » read more

Incremental System Verification
By Brian Bailey - 16 May, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief executive office for Breker Verification; Mark Olen, product marketing manager for Mentor, a Siemens Business; Jim Hogan, managing partner of Vista Ventures; Sharon Rosenberg, senior solutions archit... » read more

Complexity’s Impact On Security
By Ed Sperling - 01 May, 2019 - Comments: 0

Ben Levine, senior director of product management for Rambus’ Security Division, explains why security now depends on the growing number of components and the impact of interactions between those components. This is particularly problematic with AI chips, both on the training and inferencing side, where security problems on the training side can alter models for AI inferencing. » read more

The Case For Embedded FPGAs Strengthens And Widens
By Brian Bailey - 25 Apr, 2019 - Comments: 2

The embedded FPGA, an IP core integrated into an ASIC or SoC, is winning converts. System architects are starting to see the benefits of eFPGAs, which offer the flexibility of programmable logic without the cost of FPGAs. Programmable logic is especially appealing for accelerating machine learning applications that need frequent updates. An eFPGA can provide some architects the cover they ne... » read more

Multi-Physics At 5/3nm
By Ed Sperling - 11 Apr, 2019 - Comments: 0

Joao Geada, chief technologist at ANSYS, talks about why timing, process, voltage, and temperature no longer can be considered independently of each other at the most advanced nodes, and why it becomes more critical as designs shrink from 7nm to 5nm and eventually to 3nm. In addition, more chips are being customized, and more of those chips are part of broader systems that may involve an AI com... » read more

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