Communication Is Key To Finding And Fixing Bugs In ICs

By Ann Mutschler and Adam Kovac - 08 May, 2024 - Comments: 0

Experts at the Table: Finding and eliminating bugs at the source can be painstaking work, but it also can prevent even greater problems from developing later on. To examine the best ways to tackle this problem, Semiconductor Engineering sat down with Ashish Darbari, CEO at Axiomise; Ziyad Hanna, corporate vice president R&D at Cadence; Jim Henson, ASIC verification software product manager ... » read more

Engineers Or Their Tools: Which Is Responsible For Finding Bugs?

By Ann Mutschler and Adam Kovac - 28 Mar, 2024 - Comments: 0

Experts at the table: Finding and eliminating bugs at the source can be painstaking work, but it can prevent bigger problems later in the design flow, when they are more difficult and expensive to fix. Semiconductor Engineering sat down to discuss these issues with Ashish Darbari, CEO at Axiomise; Ziyad Hanna, corporate vice president R&D at Cadence; Jim Henson, ASIC verification software... » read more

AI Tradeoffs At The Edge

By Ann Mutschler - 15 Feb, 2024 - Comments: 0

AI is impacting almost every application area imaginable, but increasingly it is moving from the data center to the edge, where larger amounts of data need to be processed much more quickly than in the past. This has set off a scramble for massive improvements in performance much closer to the source of data, but with a familiar set of caveats — it must use very little power, be affordable... » read more

Which Data Works Best For Voltage Droop Simulation

By Ann Mutschler - 15 Jan, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about the need for the right type of data, why this has to be done early in the design flow, and how 3D-IC will affect all of this, with Bill Mullen, distinguished engineer at Ansys; Rajat Chaudhry, product management group director at Cadence; Heidi Barnes, senior applications engineer at Keysight; Venkatesh Santhanagopalan, prod... » read more

Analog Design Complicates Voltage Droop

By Ann Mutschler - 27 Dec, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about voltage droop in analog and mixed-signal designs, and the need for multi-vendor tool interoperability and more precision, with Bill Mullen, distinguished engineer at Ansys; Rajat Chaudhry, product management group director at Cadence; Heidi Barnes, senior applications engineer at Keysight; Venkatesh Santhanagopalan, product ... » read more

Managing P/P Tradeoffs With Voltage Droop Gets Trickier

By Ann Mutschler - 14 Sep, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about voltage droop/IR drop with Bill Mullen, distinguished engineer at Ansys; Rajat Chaudhry, product management group director at Cadence; Heidi Barnes, senior applications engineer at Keysight Technologies; Venkatesh Santhanagopalan, product manager at Movellus; Joe Davis, senior director for Calibre interfaces and mPower EM/IR... » read more

Programming Processors In Heterogeneous Architectures

By Ann Mutschler - 08 Jun, 2023 - Comments: 0

Programming processors is becoming more complicated as more and different types of processing elements are included in the same architecture. While systems architects may revel in the number of options available for improving power, performance, and area, the challenge of programming functionality and making it all work together is turning out to be a major challenge. It involves multiple pr... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.