Accelerate The Algorithm To Silicon Development With Stratus HLS

By Cadence - 21 Dec, 2022 - Comments: 0

Growth in demand for artificial intelligence (AI) and digital signal processing (DSP) applications, coupled with advances in semiconductor process technology, drives increasingly denser SoCs. These complex SoCs further challenge the design team’s ability to meet performance, power, and area (PPA) goals within tight time-to-market windows. We need automated and targeted solutions that efficien... » read more

Trust Assurance And Security Verification of Semiconductor IPs And ICs

By OneSpin Solutions - 22 Apr, 2020 - Comments: 0

Connected autonomous vehicles, 5G networks, Internet-of-things (IoT) devices, defense systems, and critical infrastructure use ASIC and FPGA SoCs running artificial intelligence algorithms or other complex software stacks. Vulnerable or tampered ICs can compromise the safety of people and the confidentiality, integrity, and availability of sensitive information. This paper analyzes the trust... » read more

How To Shorten Hardware-Software Development Cycles

By Frank Schirrmeister - 24 Apr, 2014 - Comments: 0

Doing more hardware-software development prior to silicon promises significant productivity and time-to-market improvements. Part of this is shifting software development “to the left,” which can compress development Last month, I blogged about “The Great Shift to the Left,” and I pointed out some of the organizational challenges associated with compressing the development cycle usin... » read more

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Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: pre-silicon development platforms

Accelerate The Algorithm To Silicon Development With Stratus HLS

Trust Assurance And Security Verification of Semiconductor IPs And ICs

How To Shorten Hardware-Software Development Cycles