Process Window Optimization Of DRAM By Virtual Fabrication

New integration and patterning schemes used in 3D memory and logic devices have created manufacturing and yield challenges. Industrial focus has shifted from the scaling of predictable unit processes in 2D structures to the more challenging full integration of complex 3D structures. Conventional 2D layout DRC, offline wafer metrology, and offline electrical measurements are no longer sufficient... » read more

Process Variation Analysis of Device Performance Using Virtual Fabrication

A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device performance. A model of a FinFET device was built using virtual device fabrication and testing. The model was subsequently calibrated on Design of Experiment corner case data that had been collected on a limited number of processed fab wafers. W... » read more

Process Window Optimization

David Fried, vice president of computational products at Lam Research, examines increasing process variation and interactions between various types of variation, why different approaches are necessary to improve yield and continue scaling. » read more