Chip Industry Week in Review

By The SE Staff - 30 May, 2025 - Comments: 1

The U.S. Commerce Department is tightening controls on EDA software sold to China by imposing additional license requirements. EDA companies are assessing the impact. Details on how broad the restrictions will be are still pending. The U.S. Federal Trade Commission (FTC) will require Synopsys and Ansys to divest key software assets — including optical, photonic, and RTL power analysis tool... » read more

Chip Industry Technical Paper Roundup: May 28

By Linda Christensen - 28 May, 2025 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=434 /] Find more semiconductor research papers here. » read more

Chip Industry Week in Review

By The SE Staff - 23 May, 2025 - Comments: 0

Podcast: imec's roadmap and a one-on-one interview with the European research house's chief strategy officer. China's Xiaomi debuted an in-house-designed 10-core mobile SoC built on a 3nm process. The company did not identify the foundry. It also announced plans to invest 50 billion yuan (~$7B) over the next decade to develop high-end smartphone chips, as part of a 200 billion yuan (~$28B) c... » read more

Doping Mechanism Of Pure Nitric Oxide In Tungsten Diselenide Transistors (Purdue, MIT, NYCU)

By Technical Paper Link - 22 May, 2025 - Comments: 0

A technical paper titled "Uncovering the doping mechanism of nitric oxide in high-performance P-type WSe2 transistors" was published by researchers at Purdue University, MIT and National Yang Ming Chiao Tung University (with support from Intel Corporation). "Atomically thin two-dimensional (2D) semiconductors are promising candidates for beyond-silicon electronic devices. However, an excessi... » read more

Chip Industry Week in Review

By The SE Staff - 25 Apr, 2025 - Comments: 0

To listen to the podcast version, click here. TSMC unveiled an unusually detailed roadmap at this week's North America Technology Symposium, including future architectures for 3D-ICs for high-performance computing and small, extremely low-power chips for AR/VR glasses, and two implementations of system-on-wafer. Fig. 1: TSMC's future packaging and stacking roadmap. Source: TSMC The ... » read more

Blog Review: Mar. 19

By Jesse Allen - 19 Mar, 2025 - Comments: 0

Cadence's Neelabh Singh explains the defined port operations of USB4 that are used to bring transmitters burst and receivers of a design under test into compliance mode and to execute tests like bit error tests, error rate tests, clock switch tests, TxFFE equalization tests, and electrical idle tests. Siemens EDA's Stephen V. Chavez examines the use of blind and buried vias in high-density i... » read more

Universities Augment Engineering Curricula To Boost Employability

By Liz Allan - 05 Feb, 2025 - Comments: 0

Increasing numbers of universities are offering semiconductor courses in their engineering programs, and also in math, physics, and business degrees. Most universities now offer a broad foundation so students can pivot to other industries during cyclical downturns, or when technology and science create entirely new and potentially lucrative opportunities, such as generative AI, advanced pack... » read more

Chip Industry Technical Paper Roundup: Jan. 20

By Linda Christensen - 20 Jan, 2025 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=398 /] Find all technical papers here. » read more

Research Bits: Jan. 20

By Jesse Allen - 20 Jan, 2025 - Comments: 0

Self-correcting memristor array Researchers at Korea Advanced Institute of Science and Technology (KAIST), Seoul National University, Sungkyunkwan University, Electronics and Telecommunications Research Institute (ETRI), and Yonsei University developed a memristor-based neuromorphic chip that can learn and correct errors, enabling it to adapt to immediate environmental changes. The system c... » read more

Transformation Of Polarons As Tellurene Becomes Thinner

By Technical Paper Link - 15 Jan, 2025 - Comments: 0

A new research paper titled "Thickness-dependent polaron crossover in tellurene" was published by researchers from Rice University, Lawrence Berkeley National Laboratory, MIT, Argonne National Laboratory, ORNL, Purdue University, and Stanford University. Abstract "Polarons, quasiparticles from electron-phonon coupling, are crucial for material properties including high-temperature supercond... » read more

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