Non-Visual Defect Inspection: The Tech of Tomorrow?

By Jeff Chappell - 12 Dec, 2013 - Comments: 0

Remember when it first became obvious that the semiconductor manufacturing industry was going to expect lithography to resolve features smaller than the wavelength of light used in the litho tools themselves? Thanks to techniques such as the use of phase shift photomasks, sub-wavelength lithography is standard in chip fabs today. It might even be viewed as “old hat,” although still an ex... » read more

Experts At The Table: Issues In Metrology And Inspection

By Mark LaPedus - 06 May, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future metrology and inspection challenges with John Allgair, senior member of the technical staff at GlobalFoundries; Kevin Heidrich, vice president of marketing and business development at Nanometrics; Robert Newcomb, executive vice president at Qcept Technologies; and Shrinivas Shetty, vice president of marketing f... » read more

Experts At The Table: Issues In Metrology And Inspection

By Mark LaPedus - 29 Apr, 2013 - Comments: 0

Experts At The Table: Issues In Metrology And Inspection

By Mark LaPedus - 18 Apr, 2013 - Comments: 0

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Qcept Technologies

Non-Visual Defect Inspection: The Tech of Tomorrow?

Experts At The Table: Issues In Metrology And Inspection

Experts At The Table: Issues In Metrology And Inspection

Experts At The Table: Issues In Metrology And Inspection