Experts At The Table: Issues In Metrology And Inspection

First of three parts: What’s missing, what’s running out of steam, and best guesses for how to tackle issues at future process nodes.

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By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future metrology and inspection challenges with John Allgair, senior member of the technical staff at GlobalFoundries; Kevin Heidrich, vice president of marketing and business development at Nanometrics; Robert Newcomb, executive vice president at Qcept Technologies; and Shrinivas Shetty, vice president of marketing for inspection systems and technology transfer at Ultratech. What follows are excerpts of that conversation.

SMD: What are the big challenges in metrology and inspection?
Allgair: As we keep scaling our devices and improved the resolutions, there is a need to not have much interaction with the measurement technique and the sample we are measuring. The information we want to get is also becoming more complex. So in the past, we had one-dimensional CD types of measurements. Now, we really want to understand both 2D and 3D information for the structures that we are measuring. We also have a desire to look at how the structure looks, versus what the design intent was. Of course, the structures are becoming more and more complex to measure. When we look at finFETs, we want to measure everything that we typically would have measured on a normal 2D CMOS device. Except now, we are trying to measure all of these parameters in 3D. That’s becoming very complex now.
Heidrich: Resolution, sample interaction, and complexity drive us, as well as 3D requirements. Top-down measurements, and how wide something is, are important now. How tall is the structure and the undercut are important, as well. The idea of measuring more parameters on a given sample is driving our tool technology and software. But also important, the users of the tools have to deal with even more information, whether how they deal with it for process control or how they collect it from a metrologist point of view. In addition, there are a lot of new architectures coming up in several different areas and all at the same time. One of our challenges is to come up with comprehensive solutions for finFET metrology and 3D ICs for stacking.
Newcomb: The defects continue to get smaller and smaller. But the complexity of those defect issues is being driven by a proliferation of new materials throughout the process at the front-end-of-the-line and the back-end-of-the-line. So when you combine the materials, the device structures and the process technology, we have the continuing challenge of physical defect inspection. But now, we are finding more and more non-visual defects becoming a major part of the yield-critical defects in the fab. Being able to detect those non-visual defects is becoming important, especially at the advanced process nodes.
Shetty: We all agree that resolution is the biggest issue out there. As these device sizes shrink, they are behaving very differently. The information you are getting from these inspection tools is not correlating. Customers are also seeing big yield issues, mainly at the edges of the wafer. And a lot of these inspection and metrology tools are limited on the edge of devices. On the device side, there are two big challenges. The devices are going in vertical dimensions with 3D structures, such as finFETs. On the horizontal direction, customers are going from 300mm to 450mm wafers. This changes the dimensions both in the vertical and horizontal direction, offering more and more challenges in terms of stress, overlay, lithography and CD. We are also bringing in high-stress films like high-k, silicon germanium and thin films. The challenge is can the current inspection and metrology tools keep up with all of these changes taking place.

SMD: Are the existing metrology tools keeping up or do we need new breakthroughs?
Allgair: If you look at the tools available right now, we are primarily controlling the line with the things everyone is used to. We have the CD-SEM, scatterometry, and we have the typical overlay techniques. We use a little AFM. In terms of inspection, we have brightfield inspection and some e-beam inspection. When we look across that tool set, we do see the need for improvements as we move to smaller device dimensions. On the imaging side, we need increased resolution in order to measure some of these features. We are seeing improvements in the CD-SEM. It might be able to get us where we want to go. There may be a need to have a higher resolution-capable tool. We would like that tool not to damage the feature if at all possible. On the scatterometry side, we think that technique is pretty extendable. We start to run into issues with some of the materials interactions. Then, we question the extensibility. There is some work now that says it may extend to the 9nm node before it starts to lose some steam. We have looked at perhaps using another technique like X-ray to extend it.
Heidrich: For the most part, we are doing two things. We are taking tools like our OCD tool and continuously improving the signal to noise for a given configuration. We are also adding more data channels to the tool. We are pretty confident following those approaches we will continue to extend down to many future nodes, and well below normal diffraction limits.

SMD: What about inspection and overlay?
Allgair: On the inspection side, brightfield has some steam left, but it has become very challenged. The idea of having e-beam inspection helps solve some of the resolution problems. But we have a throughput challenge there. So then, we have the concept of multi-column, e-beam inspection. If we could make it work, and have the throughputs that we want, that’s attractive to us. If I talk about overlay, the idea of measuring overlay right off the device structure could be very useful.
Newcomb: We think non-visual defect inspection is the next big thing on the horizon. Most of these leading-edge fabs will say that up to 30% of their yield problems have a ‘no defect found’ category. That basically says I know I have a defect issue at the end of the line and I can see that in my yield maps, but I have no corresponding or matching inspection data from the process line from all of these optical inspection tools or e-beam. Existing tools can address 70% of my defect problems. But I still have 30% of my yields, in which I don’t have a good method to attack from an inspection and yield engineering perspective. That’s where non-visual defect inspection can play a major role.
Shetty: Traditional tools from KLA and ASML do a good job of measuring the targets as a measurement itself. While they do a good job bringing information to the scanners, we are focusing on a tool that gives you non-destructive, high-resolution on the edge of the wafer. And it mainly tells you information on the stress, the shape and distortion. The technology we offer does not replace the traditional overlay tools from KLA and ASML. It’s actually a complementary technology.

SMD: What other breakthroughs are needed?
Heidrich: We see a growing demand for in-line, on-device compositional metrology. That’s an underserved market right now. There are very few tools that have the spot size, resolution and the discrimination that satisfy customers out there.
Allgair: We have been pushing the idea of hybrid metrology, which is the idea of using data from previous process steps. So now, your downstream measurement tool has at least some information coming in about the wafer to make your measurements a little bit more accurate. This is one of the things that could help solve this overall problem of trying to determine what the feature looks like in 3D. From a user perspective, I would like to have a complete picture of what it is I am measuring in the 3D space. I want to know where every avenue is. I want to know where it is located in the matrix, what type it is, and what the electron activity is. That’s ultimately what we want to know. We are still a long way from that. That seems to be kind of the new Holy Grail, so to speak, of metrology.