Non-Visual Defect Inspection: The Tech of Tomorrow?

The chip industry is conservative when it comes to adopting new metrology and inspection. Will it ultimately see NVD inspection as a wunderkind, or an also-ran?


Remember when it first became obvious that the semiconductor manufacturing industry was going to expect lithography to resolve features smaller than the wavelength of light used in the litho tools themselves?

Thanks to techniques such as the use of phase shift photomasks, sub-wavelength lithography is standard in chip fabs today. It might even be viewed as “old hat,” although still an expensive old hat.

Whether non-visual defect (NVD) inspection follows a similar trend remains to be seen. This is perhaps especially true in light of the history of metrology and inspection technology. Chipmakers always have been loathe to spend money on these often expensive tools and processes unless it proves indispensable in production. That explains why historical adoption rates of today’s standard metrology and inspection tools tend to have long ramps.

Still, it’s clear that as the industry begins to get serious about the forthcoming 14nm and 10nm nodes, NVDs, such as sub-monolayer residues and contaminants, have the potential to become increasingly problematic. One could argue they already are. But the key words here are non-visual and sub-monolayer, as in “sub-atomic.”

Chip manufacturing in the age of the electron
Generally speaking, device shrinks have proven problematic for years now. That’s nothing new and hasn’t been at least since R&D got underway for the 0.13-micron node. But things are getting really, really tiny now, not to mention complex—so much so that the industry is going to have to start worrying about specific electrons and Heisenberg.

“It hasn’t been uncommon with the 28nm and the 20nm transition where you get a device and everything looks great, but it doesn’t work right. You have, maybe for lack of a better term, a current flow problem,” said Dean Freeman, a semiconductor equipment analyst with Gartner Inc.

Freeman wasn’t talking about NVDs specifically, but commenting more generally on the challenges the industry faces at the 14nm and 10nm nodes and beyond, as the end of Moore’s Law creeps up on the horizon, along with exotic things like single-electron transistors.

The industry is probably going to see more problems like the one he described above, along with the need to be able to detect things that aren’t immediately understood. “We’re getting to the point where our modern measurements are getting past Heisenberg’s uncertainty principle,” Freeman said.

“One of the things people have to realize is, it’s just a lot more difficult to manufacture, even at sub-30nm, than people first thought,” said Bob Johnson, another analyst with Gartner who specializes in the metrology and defect inspection market segments. He noted that even a juggernaut such as Intel, with its deep pockets and advanced R&D efforts, was later than expected with its first sub-22nm chip.

In today’s advanced manufacturing fab line, a defect “can be something as subtle as something like two lines too close together that generate a certain amount of heat, which then throws off a timing circuit,” Johnson said.

As for NVDs, are they going to become more of a problem? Will the industry need NVD inspection tools on production lines, beyond the R&D and pilot lines? It’s too early to say just yet. Nevertheless there is some interesting and even compelling data out there.

So how do you see an NVD?
So if a defect is non-visual, i.e., you can’t see it because it doesn’t reflect or otherwise scatter light, how do you detect it? How do you “see” sub-monolayer contamination?

Currently there is only one company on the market offering NVD inspection tools to the chip industry: Qcept Technologies Inc. At the heart of Qcept’s tools is the concept of a vibrating Kelvin probe, a vibrating capacitor device that measures changes in the work function or potential in surface chemistry — without contacting the surface. Rather than vibrating a probe tip over a wafer surface, Qcept’s ChemetriQ scans the entire surface of a wafer, measuring differentials in work function. Its tools can scan a 300mm wafer in four minutes, according to the company.

Spun out of the Georgia Institute of Technology, the company announced its first beta site projects in 2011, one at a leading-edge logic fab and the other at a leading-edge memory fab; both involved inspection of 3X-nm production wafers. Since then it has placed systems at five of the top six chipmakers as determined by sales (not including fabless companies, naturally).

One of those chipmakers is South Korea’s Samsung Electronics. Samsung and Qcept published a joint paper earlier this year detailing the company’s use of Qcept’s ChemetriQ tool to identify a post-wet clean residue that was ultimately causing pitting defects in a later gate oxide process. The residue defect correlated with a known yield problem at end of line (EOL) test. Notably, while Samsung said it suspected the defect was occurring at the front-end of line gate module process, there was no matching defect pattern identified during optical inspection. The company used ChemetriQ inspection at several process steps in the gate and spacer module process, including post-gate lithography, post-gate etch and clean, post-spacer deposition and post-spacer etch and ash clean.

The resulting inspection data detected spots of increased work function in areas of the wafer that corresponded with the location of die failing at EOL test. Ultimately NVD inspection illustrated that the way a batch clean tool was handling the wafer was leaving unwanted residue on part of the wafer; among the most promising solutions was switching to a linear, single-wafer clean tool which enabled a more uniform post-clean surface and a significant yield increase at final test, according to Samsung.

Problems like the one discussed in the Samsung paper are not uncommon, according to Qcept. The company has had customers with 20 to 30 percent yield problems at end of line with no corresponding defect data, according to Robert Newcomb, executive vice president at Qcept. That’s where a lot of the time NVD inspection helps find the additional yield, when there is no corresponding optical defect inspection data, he said.

In October the company published a paper with Applied Materials Inc.’s Asia Product Development Center in Singapore and the Institute of Microelectronics in Singapore in which the companies used Qcept’s inspection technology to detect surface contamination within a chemical mechanical polarization (CMP) process used to reveal through-silicon vias (TSVs). The fact that Applied Materials turned to Qcept for CMP process development help perhaps speaks volumes, particularly given that Applied has its own optical defect inspection division — detecting NVDs is clearly a new thing.

While residues are one category of NVD, another is process-induced charge, according to Newcomb. “We have found that charge can result in yield failure and yield defectivity in many ways — electrostatic charge, discharge in the wafer — it can blow out the gate oxide fabbed three weeks ago,” he said. “Charge can result in electrochemical defects too.”

Charge problems tend to result from wet process steps, Newcomb noted. “Any process where you are doing a wet process to the surface of the wafer with different chemistries can result in these charge events,” he said. It is one area in which Qcept’s customers are focusing on in particular.

Wafer cleaning is incidentally one of the most common and repeated steps in a fab line. Some 200 steps can be involved with surface prep and cleaning with the fabrication of a complex device. Given the increasing use of exotic materials in semiconductor fabrication, that number is likely to grow at future nodes. “From that perspective, for wet cleans and surface prep, it’s more than just particles,” Newcomb said.

Future inspection tech or perfect future inspection tech?
Nevertheless, to say NVDs are a widespread phenomenon, or will be, or rather that NVD inspection is the wave of the inspection future — it’s too early to make that call. As Gartner’s Johnson noted, 30% yield problems at advanced nodes is hardly unusual. In fact some of the large complex die that appeared at 28nm node were rumored to have production yields in the 40% range.

Again, when it comes to metrology and inspection, chipmakers are loathe to spend money on the tools and add the steps in production. Any time there is a new metrology technology, it goes into the R&D area first before it gets adopted in production. Chipmakers have to be convinced that the problems illustrated in R&D are problems that are not just solved then and there, and instead must be monitored in production, Johnson said. And what if NVDs do prove a recurring problem in the production fab? “Then you would have to put some (NVD) inspection steps at critical points in the fab,” he said.

Johnson noted there have been promising metrology and inspection technologies in the past that failed to find their way into mainstream production, such as integrated metrology. In that case it proved too expensive and not absolutely necessary.

On the other hand, there is the example of optical critical dimension (CD) metrology technology. It had a long road to adoption. Like NVD inspection tech today, at the time optical CD inspection was a brand-new technology and it took the industry a while to figure out how to use it. Today, however, it’s an important part of the fab line and the metrology tool market.

As for NVD inspection technology and Qcept, time will tell. But it would seem that at least for the likes of Applied and Samsung, the evidence thus far is compelling.

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