Experts At The Table: Issues In Metrology And Inspection

Second of three parts: Litho challenges; thinner resists; overlay and process effects; finFETs; stacked die.


By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future metrology and inspection challenges with John Allgair, senior member of the technical staff at GlobalFoundries; Kevin Heidrich, vice president of marketing and business development at Nanometrics; Robert Newcomb, executive vice president at Qcept Technologies; and Shrinivas Shetty, vice president of marketing for inspection systems and technology transfer at Ultratech. What follows are excerpts of that conversation.

SMD: From your vantage point, what are the challenges for lithography?
Allgair: Among the challenges are resolution and the interaction of the metrology with the resists we are trying to measure. Of course, the resist materials are getting thinner and thinner. And this creates its own set of challenges both from a resolution and an interaction point of view. Also, when moving to new materials, there is the measurement piece. As I mentioned before, we want more 2D and 3D information from the resists. In addition, we want to compare the resists versus what we did with the design. And we are trying to look for the defects. And with overlay, we are seeing challenges there, as well—everything from the sheer volume of the measurements we have to take, to the ability of the overlay targets to really predict what’s going on within the circuit itself. That frequently drives the need for more targets and with in-die targets. And that gets further complicated by the fact that your targets can be impacted by your processing, so you wind up having process interactions that are involved in the overlay target measurements. Somehow you need to take those interactions out to understand where your overlay is.
Heidrich: Litho is driving resolution, overlay and process effects. From each of those, from a CD point of view, we see OCD is the method of choice. Regardless of the techniques used, customers are dealing with measurements on more complex structures in a design. So the question is how many types of structures do you measure in production to track OPC corrections and other complex interactions, as well as additional complexity in the resist patterns themselves? You could end up seeing a double pattern litho resist or other type of litho resist. For overlay, there is a data explosion. The data is going up. At the same time, target size is going down.
Newcomb: Edge inspection is an area of interest. There is a need to combine your wafer inspection and edge inspection and do multi-analysis and multi-channel inspection. Regarding the resists, customers are seeing interactions, for example, in the CD-SEM and e-beam. This is making it difficult to make good and accurate measurements. In the past, it was all about beam alignment, emission and spot size in order to make a measurement for a via hole as one example. Now, in litho, that resist has a charge and creates an electric field that directly impacts the ability to make those critical measurements.
Shetty: As the device sizes are shrinking, the overlay budgets are shrinking. Right now, at 20nm and 16nm, the overlay budget is around 10nm or 8nm. But because of all the issues the customers are having, such as EUV implementation, customers are going with unique schemes like double patterning and triple patterning. What happens is that 10nm budget gets cut by half or one-third. So every part of the overlay budget gets impacted. There are three parts of the overlay budget. There is one that is coming from the overlay tool from the scanner. The second one is coming from the reticle. The third one is coming from the wafer itself. These are wafer-based distortions that the scanner can’t fix. Regarding the overlay tool, traditional tools like Archer and others measure the overlay. As the device sizes are shrinking, the targets are behaving more and more differently than the devices themselves. Customers are left with two choices. Either they can increase the number of targets on the wafer and then take a hit on throughput and have higher costs. Or, they can find a different way to measure these wafers. For example, by using limited targets on the wafer, they will not get all of the information they need for the scanner to fix the wafer.

SMD: What about finFETs?
Newcomb: 3D structures like finFETs not only require more metrology and inspection steps, but they involve a lot more complexity. You are not just looking at the information in the x, y, and z axis, but also at the atomic level of x, y and z. You are asking things like how does that device come together? What is the structure of that device? Does it meet the specs? We are starting to see some interesting interactions with existing process tools types, whether they are across the edge or wet cleaning. When you use existing technologies, and try to build 3D structures, you are getting defect signatures that we’ve never seen before from net Vdd perspective. You also have all of these defectivity models coming forward and you have to deal with them.
Allgair: Going to 3D has created numerous challenges for us. We see tenfold measurement problems as we go to 3D. A lot of things you see in 2D tend to get amplified as we go to these 3D structures. In an x, y and z matrix, you need to ask: ‘The atoms are there, but are they the ones you want? Are they electrically active or not?’ We are trying to use the same tooling that we currently have available. You will see the CD-SEM, OCD, and the overlay tools you are familiar with. With finFETs, we can do some things, such as CD, height, profile, spacer, and thickness. Some of these applications can be done using scatterometry or CD-SEM or a combination of that data set. Then, we see some real challenges when it comes to compositional analysis. In finFET devices, we’ve got compositional measurements like SiGe with a percentage of germanium and a percentage of boron on a 3D structure. That’s a very complex measurement. Finally, we try and do measurements on test structures. The test structures don’t always mimic what’s actually taking place on your device. That really adds to the complexity of trying to manufacture finFETs in a stable manner.

SMD: What are some of the issues with stacked 2.5D and 3D devices?
Newcomb: As we turn to the 3D packaging world, and we think about stacked memory or memory on logic, we have techniques like traditional optical inspection. Although it will be important for 3D packaging and 3D ICs, you have to be concerned about a whole new class of things like sub-monolayer metallic contamination within the device area. If these wafers need to be thin, and I need to expose the TSVs, I start seeing copper defectivity and sub-monolayer issues. Now, I am trying to stack multiple known-good die. As we package these known-good die in 3D structures, and if you have one mistake like sub-monolayer copper residue, that will make multiple known-good die no longer any good.
Heidrich: Plus, you hand off a known good wafer to someone and then you need to integrate it. In effect, you are doing double metrology and double inspection. And then in the process itself, there is a lot of complexity we address in terms of TSVs. Metrology and inspection for that whole flow must be addressed for cost, performance and reliability.
Allgair: If I look at the 3D TSV side, the idea of stacking structures has created a need for new tools. We have been looking at new techniques, which should work out reasonably well. We are making pretty good progress.

Leave a Reply

(Note: This name will be displayed publicly)