tag: Rambus

Chip Challenges In The Metaverse
By Ed Sperling - 24 Oct, 2022 - Comments: 0

The metaverse is pushing the limits of chip design, despite uncertainty about how much raw horsepower these devices ultimately will require to deliver an immersive blend of augmented, virtual, and mixed reality. The big challenge in developing these systems is the ability to process mixed data types in real time while the data moves uninterrupted at lightning speed. That requires the integra... » read more

Week In Review: Design, Low Power
By Marie C. Baca - 21 Oct, 2022 - Comments: 0

Tools and IP Electronic system design revenue hit a record $3.75 billion in the second quarter, according to a report from ESD Alliance, a SEMI Technology Community. That number represents a 17.5% year-over-year increase. Walden C. Rhines, the report’s executive sponsor, said it was the largest such jump in over a decade and that all product categories and geographic regions recorded second ... » read more

HBM3 In The Data Center
By Ed Sperling - 17 Oct, 2022 - Comments: 0

Frank Ferro, senior director of product management at Rambus, talks about the forthcoming HBM3 standard, why this is so essential for AI chips and where the bottlenecks are today, what kinds of challenges are involved in working with this memory, and what impact chiplets and near-memory compute will have on HBM and bandwidth.     » read more

Foundational Changes In Chip Architectures
By Brian Bailey - 13 Oct, 2022 - Comments: 5

We take many things in the semiconductor world for granted, but what if some of the decisions made decades ago are no longer viable or optimal? We saw a small example with finFETs, where the planar transistor would no longer scale. Today we are facing several bigger disruptions that will have much larger ripple effects. Technology often progresses in a linear fashion. Each step provides incr... » read more

Designing A Better Clock Network
By Ann Mutschler - 13 Oct, 2022 - Comments: 0

Laying the proper clock network architecture foundation makes all the difference for the best performance, power, and timing of a chip, particularly in advanced node SoCs packed with billions of transistors. Each transistor, which acts like a standard cell, needs a clock. An efficient clock network should ensure the switching transistors save power. In today’s advanced nodes, when a design... » read more

Dealing With Heat In Near-Memory Compute Architectures
By Karen Heyman - 13 Oct, 2022 - Comments: 0

The explosion in data forcing chipmakers to get much more granular about where logic and memory are placed on a die, how data is partitioned and prioritized to utilize those resources, and what the thermal impact will be if they are moved closer together on a die or in a package. For more than a decade, the industry has faced a basic problem — moving data can be more resource-intensive tha... » read more

Beyond Autonomous Cars
By Marie C. Baca - 12 Oct, 2022 - Comments: 0

As the automotive industry takes a more measured approach to self-driving cars and long-haul trucks for safety and security reasons, there is a renewed focus on other types of vehicles utilizing autonomous technology. The list is long and growing. It now includes autonomous trains, helicopters, tractors, ships, submarines, drones, delivery robots, motorcycles, scooters, and bikes, all of whi... » read more

EVs Raise Energy, Power, And Thermal IC Design Challenges
By Ann Mutschler - 06 Oct, 2022 - Comments: 0

The transition to electric vehicles is putting pressure on power grids to produce more energy and on vehicles to use that energy much more efficiently, creating a gargantuan set of challenges that will affect every segment of the automotive world, the infrastructure that supports it, and the chips that are required to make all of this work. From a semiconductor standpoint, improvements in th... » read more

CXL 3.0: From Expansion To Scaling
By Danny Moore - 06 Oct, 2022 - Comments: 0

At the Flash Memory Summit in August, the CXL Consortium released the latest, and highly anticipated, version 3.0 of the Compute Express Link (CXL) specification. This new version of the specification builds on previous generations and introduces several compelling new features that promise to increase data center performance and scalability, while reducing the total cost of ownership (TCO). ... » read more

Testing Chips For Security
By Jeff Goldman - 06 Oct, 2022 - Comments: 0

Supply chains and manufacturing processes are becoming increasingly diverse, making it much harder to validate the security in complex chips. To make matters worse, it can be challenging to justify the time and expense to do so, and there’s little agreement on the ideal metrics and processes involved. Still, this is particularly important as chip architectures evolve from a single chip dev... » read more

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