tag: Real Intent

The Week in Review: System-Level Design
By Ed Sperling - 15 Nov, 2013 - Comments: 0

Cadence unveiled its next-gen power signoff tool, this one based upon parallel execution across multiple processors. The result is 10x speed improvement, according to the company. The signoff solution already is certified for TSMC’s 16nm finFET process for IR drop analysis and EM rule compliance, two of the big concerns with finFETs. Synopsys teamed up with CEVA to improve PPA for CEVA’s... » read more

Blog Review: Nov. 13
By Ed Sperling - 13 Nov, 2013 - Comments: 0

Synopsys’ Brent Gregory digs into optimal paths—in this case between the bakery, the library and another store. This is the classic traveling salesman equation, but with a large sales staff and lots of stops. Mentor’s Michael Ford points to the gap between supply-chain and shop-floor management solutions. This is yet another example of thinking outside the package—and maybe the enti... » read more

Experts At The Table: The Future Of Verification
By Ed Sperling - 11 Nov, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the future of verification with Janick Bergeron, Synopsys fellow; Harry Foster, chief verification scientist at Mentor Graphics; Frank Schirrmeister, group director of product marketing for the Cadence System Development Suite; Prakash Narain, president and CEO of Real Intent; and Yunshan Zhu, vice president of new technologies at Atrenta. What foll... » read more

Are Designers’ X-Analysis Needs Different From Verification Engineers?
By Lisa Piper - 11 Nov, 2013 - Comments: 0

The propagation of unknown (X) states has become a more pressing issue with the move toward billion-gate SoC designs. Besides the sheer complexity of these designs, the common use of complex power management schemes increase the likelihood of an unknown ‘X’ state in the design translating into a functional bug in the final chip. This article describes a methodology that enables design an... » read more

Experts At The Table: The Future Of Verification
By Ed Sperling - 04 Nov, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the future of verification with Janick Bergeron, Synopsys fellow; Harry Foster, chief verification scientist at Mentor Graphics; Frank Schirrmeister, group director of product marketing for the Cadence System Development Suite; Prakash Narain, president and CEO of Real Intent; and Yunshan Zhu, vice president of new technologies at Atrenta. What foll... » read more

Blog Review: Oct. 30
By Ed Sperling - 30 Oct, 2013 - Comments: 0

Mentor’s Nazita Saye has stumbled on a phone that you can build yourself from various components. When something breaks, you simply change out what’s broken. Wasn’t that the concept behind the original Volkswagen Beetle? Cadence’s Brian Fuller launches into the discussion about 16nm headaches, including finFET parasitics, pin access and wire resistance. Looks like the transition to f... » read more

Experts At The Table: The Future Of Verification
By Ed Sperling - 24 Oct, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the future of verification with Janick Bergeron, Synopsys fellow; Harry Foster, chief verification scientist at Mentor Graphics; Frank Schirrmeister, group director of product marketing for the Cadence System Development Suite; Prakash Narain, president and CEO of Real Intent; and Yunshan Zhu, vice president of new technologies at Atrenta. What foll... » read more

Start Verification Early To Avoid Pitfalls Later
By Ann Mutschler - 24 Oct, 2013 - Comments: 1

It is well understood – at least from a theoretical point of view – that design verification should start as early as possible. The reality is that that doesn’t always happen for a variety of reasons such as enormous time to market pressure, too many new features to add, lack of foresight and discipline among other things. But progress is being made. Harry Foster, chief scientist for v... » read more

Trending Back To ASICs
By Ann Mutschler - 24 Oct, 2013 - Comments: 0

True to its cyclical nature, the semiconductor industry is swinging back toward ASICs from more diversified approaches such as FPGAs. This dynamic is evident at companies such as Apple. “At one point we thought Apple was being a contrarian,” said Drew Wingard, CTO at Sonics. “Everybody else on the systems side was shedding their silicon people. The easiest counterpoint to what Apple wa... » read more

A Night to Remember: EDA Back to the Future
By Graham Bell - 24 Oct, 2013 - Comments: 0

I had the pleasure to attend the EDA: Back to the Future event at the Computer History Museum on Oct. 16.   There were over 230 guests to raise money for the EDA Oral History Project at the Museum.   There were industry luminaries honored at the event, and I did red carpet interviews with many of them as they arrived including Joe Costello, Simon Segars, and Penny Herscher.  As I did the i... » read more

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