tag: ReRAM

Key Recovery for Content Protection Using Ternary PUFs Designed with Pre-Formed ReRAM
By Technical Paper Link - 19 Mar, 2022 - Comments: 0

RESEARCH PAPER Abstract "Physical unclonable functions, embedded in terminal devices, can be used as part of the recovery process of session keys that protect digital files. Such an approach is only valuable when the physical element offers sufficient tamper resistance. Otherwise, error correcting codes should be able to handle any variations arising from aging, and environmentally induce... » read more

Comprehensive Model of Electron Conduction in Oxide-Based Memristive Devices
By Technical Paper Link - 03 Feb, 2022 - Comments: 0

Abstract "Memristive devices are two-terminal devices that can change their resistance state upon application of appropriate voltage stimuli. The resistance can be tuned over a wide resistance range enabling applications such as multibit data storage or analog computing-in-memory concepts. One of the most promising classes of memristive devices is based on the valence change mechanism in oxide... » read more

Making PUFs Even More Secure
By Bryon Moyer - 06 Jan, 2022 - Comments: 0

As security has become a must-have in most systems, hardware roots of trust (HRoTs) have started appearing in many chips. Critical to an HRoT is the ability to authenticate and to create keys – ideally from a reliable source that is unviewable and immutable. “We see hardware roots of trust deployed in two use models — providing a foundation to securely start a system, and enabling a se... » read more

Power/Performance Bits: Nov. 16
By Jesse Allen - 16 Nov, 2021 - Comments: 0

Light-emitting memory Researchers from Kyushu University and National Taiwan Normal University propose a 'light-emitting memory' based on a perovskite that can simultaneously store and visually transmit data. The team used the idea in conjunction with resistive RAM (RRAM), in which states of high and low resistance represent ones and zeros. "The electrical measurements needed to check the r... » read more

More Errors, More Correction in Memories
By Bryon Moyer - 09 Nov, 2021 - Comments: 1

As memory bit cells of any type become smaller, bit error rates increase due to lower margins and process variation. This can be dealt with using error correction to account for and correct bit errors, but as more sophisticated error-correction codes (ECC) are used, it requires more silicon area, which in turn drives up the cost. Given this trend, the looming question is whether the cost of ... » read more

New Memories Add New Faults
By Bryon Moyer - 07 Sep, 2021 - Comments: 1

New non-volatile memories (NVM) bring new opportunities for changing how we use memory in systems-on-chip (SoCs), but they also add new challenges for making sure they will work as expected. These new memory types – primarily MRAM and ReRAM – rely on unique physical phenomena for storing data. That means that new test sequences and fault models may be needed before they can be released t... » read more

Intermittent Undefined State Fault in RRAMs
By Technical Paper Link - 03 Sep, 2021 - Comments: 1

Abstract: " Industry is prototyping and commercializing Resistive Random Access Memories (RRAMs). Unfortunately, RRAM devices introduce new defects and faults. Hence, high-quality test solutions are urgently needed. Based on silicon measurements, this paper identifies a new RRAM unique fault, the Intermittent Undefined State Fault (IUSF); this fault causes the RRAM device to intermittently c... » read more

FORMS: Fine-grained Polarized ReRAM-based In-situ Computation for Mixed-signal DNN Accelerator
By Technical Paper Link - 19 Aug, 2021 - Comments: 0

Abstract: "Recent work demonstrated the promise of using resistive random access memory (ReRAM) as an emerging technology to perform inherently parallel analog domain in-situ matrix-vector multiplication—the intensive and key computation in deep neural networks (DNNs). One key problem is the weights that are signed values. However, in a ReRAM crossbar, weights are stored as conductance of... » read more

HBM Takes On A Much Bigger Role
By Brian Bailey - 13 May, 2021 - Comments: 1

High-bandwidth memory is getting faster and showing up in more designs, but this stacked DRAM technology may play a much bigger role as a gateway for both chiplet-based SoCs and true 3D designs. HBM increasingly is being viewed as a way of pushing heterogenous distributed processing to a completely different level. Once viewed as an expensive technology that only could be utilized in the hig... » read more

DRAM’s Persistent Threat To Chip Security
By Bryon Moyer - 10 Feb, 2021 - Comments: 0

A well-known DRAM vulnerability called "rowhammer," which allows an assailant to disrupt or take control of a system, continues to haunt the chip industry. Solutions have been tried, and new ones are being proposed, but the potential for a major attack persists. First discovered some five years ago, most of the efforts to eliminate the "rowhammer" threat have done little more than mitigate t... » read more

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